AMD AMD-K6-2/400 User Guide - Page 317
Signal Switching Characteristics
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 16 Signal Switching Characteristics The AMD-K6-2E+ processor signal switching characteristics are presented in Table 62 through Table 71 on the following pages. Valid delay, float, setup, and hold timing specifications are listed. These specifications are provided for the system designer to determine if the timings necessary for the processor to interface with the system logic are met. s Table 62 on page 296 and Table 63 on page 297 contain the switching characteristics of the CLK input. s Table 64 on page 298 through Table 67 on page 304 contain the timings for the normal operation signals. s Table 68 on page 306 and Table 69 on page 307 contain the timings for RESET and the configuration signals. s Table 70 on page 308 and Table 71 on page 308 contain the timings for the test operation signals. All signal timings provided are: s Measured between CLK, TCK, or RESET at 1.5 V and the corresponding signal at 1.5 V-this applies to input and output signals that are switching from Low to High, or from High to Low s Based on input signals applied at a slew rate of 1 V/ns between 0 V and 3 V (rising) and 3 V to 0 V (falling) s Valid within the operating ranges given in "Operating Ranges" on page 286 s Based on a load capacitance (CL) of 0 pF Chapter 16 Signal Switching Characteristics 295