AMD AMD-K6-2/400 User Guide - Page 358

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 coherency 222 external address strobe signal 109 hold signal 97 inquire cycles 100, 174 parity 98-99 strobe copy signal 96 strobe signal 96 valid 109 arbitration cycles, inquire and 168 backoff 182 byte enable signals 100 cycles 153-197 aligned transfers 129 definitions (table 142 order during misaligned I/O transfers (table 167 order during misaligned memory transfers (table). . 160 special 142, 190 data 97, 103, 174 AHOLD restriction 180 aligned transfers 129 byte enables 100 D[63:0 107 memory reads and writes 158 misaligned transfers 129, 184 parity 108, 125 state 156 transition 157 frequency signals 101 hold request signal 115 lock signal 120 request signal 104 states address 156 data 156 data-NA# requested 156 idle 156 pipeline address 156 pipeline data 157 state machine (figure 155 transition 157 BVC Field 146 definition (table 147 BVCM Bit 147 BYPASS Instruction 260 Bypass Register (BR 259 C Cache 263 branch target 26 burst writeback cycles 164 cacheable access 105 coherency 222 writeback 227 writethrough 227 control 229 data cache 16 disabling 46, 211, 251, 263 enabling 119 flushing 112, 191 inhibiting 251, 263 inquire cycles 168, 174, 178 inquire cycles (table 225 instruction cache 16 instruction fetch and decode 17 instruction prefetch 16-17, 220 L1 cache cache-line replacement 214 coherency states 227 data cache 16 data cache line (figure 207 instruction cache 16 instruction cache line (figure 207 internal snooping 223 organization 205 write allocate 215 L2 cache cache line (figure 207 cache-line replacement 214 data reads 266 direct access 50 disabling for debug 47 EDX register content 265 Level-2 Cache Array Access Register (L2AAR 50 organization 205 RDMSR instruction effect 265 sector and line organization (figure 265 tag array testing 213, 264 tag information (figure 52 tag or data location (figure 51 testing 264 WRMSR instruction effect 265 L3 cache debugging 263 PCD signal 264 testing 263 Level-2 Cache Array Access Register (L2AAR 264 -line fills 213, 264 -line replacement 214, 224 masking cache accesses with A20M 227 MESI states in the data 207 operation 208 organization 205 organization (figure 206 predecode bits 16-17, 208 prefetching 16-17, 220 sector organization 16 sector organization (figure 16 signals 211 snooping 223 states 221 states (table 225 Super7 platform support 8 total internal 1 TR12 46 translation lookaside buffers (TLBs 205 write allocate 215 write cycle order 229 write merge buffer 229 write to a cacheable page 216 writeback 12, 16 writethrough 227 CACHE# Signal 105 generation (table 210 Capacitance 288 capacitor placement 292 large capacitive loads 293 336 Index