AMD AMD-K6-2/400 User Guide - Page 149
RESET (Reset
View all AMD AMD-K6-2/400 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 149 highlights
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 5.40 RESET (Reset) Pin Attribute Summary Input When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state including its pipelines and caches, the floating-point state, the MMX state, the 3DNow! state, and all registers, and then the processor jumps to address FFFF_FFF0h to start instruction execution. The FLUSH# signal is sampled during the falling transition of RESET to invoke the Three-State Test mode. Sampled RESET is sampled as a level-sensitive input on every clock edge. System logic can drive the signal either synchronously or asynchronously. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC reach specification before it is negated. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. Chapter 5 Signal Descriptions 127