AMD AMD-K6-2/400 User Guide - Page 343
Pin Designations
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 18 Pin Designations This chapter includes pin connection diagrams and pin designation tables for each of two packages, the Ceramic Pin Grid Array (CPGA) and the Organic Ball Grid Array (OBGA). The pin designation diagrams include the following annotations: Control/Parity Pins VSS Pins VCC2 Pins VCC3 Pins Data Pins Address Pins T Test Pins NC, INC (Internal No Connect) Pins RSVD (Reserved) Pins Note that the OBGA package includes additional pins not supported on the CPGA package. Table 74 shows the pin differences between the two packages. Chapter 18 Table 74. Pin Differences Between the CPGA and OBGA Packages Pin CPGA Package OGBA Package Comment VCC2DET Supported Not supported VCC2H/L# Supported Not supported VID[4:0] Supported on lowpower versions only Supported on lowpower versions only These pins are no-connects (NC) on standard-power versions for both packages. VCC2 28 37 VCC3 32 26 VSS 68 99 No Connects 131 82 131 82 Internal No Connects 7 1 Reserved 14 16 Notes: 1. Standard-power versions only, since the VID[4:0] outputs are not supported. 2. Low-power versions only. Pin Designations 321