AMD AMD-K6-2/400 User Guide - Page 212
Special Bus Cycles, Basic Special Bus, Cycle
View all AMD AMD-K6-2/400 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 212 highlights
Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 7.6 Special Bus Cycles The AMD-K6-2E+ processor drives special bus cycles that include the following: s Stop grant s Enhanced power management s Flush acknowledge s Cache writeback invalidation s Halt s Cache invalidation s Shutdown During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and A[31:3] are driven to differentiate among the special cycles, as shown in Table 33. Note that the system logic must return BRDY# in response to all processor special cycles. Table 33. Encodings for Special Bus Cycles BE[7:0]# A[4:3]1 Special Bus Cycle FBh 10b Stop Grant BFh 00b EPM Stop Grant2 EFh 00b Flush Acknowledge F7h 00b Writeback FBh 00b Halt FDh 00b Flush FEh 00b Shutdown Notes: 1. A[31:5] = 0 2. Supported on the low-power versions only. Cause STPCLK# sampled asserted A dword access is made to the EPM 16-byte I/O block and the GSBC bit of the EPMR register is set to 1 FLUSH# sampled asserted WBINVD instruction HLT instruction INVD,WBINVD instruction Triple fault Basic Special Bus Cycle Figure 77 on page 191 shows a basic special bus cycle. The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h, which indicates that the special cycle is a halt special cycle (See 190 Bus Cycles Chapter 7