AMD AMD-K6-2/400 User Guide - Page 49
Software Environment, 3.1 Registers, Registers
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 3 Software Environment This chapter provides a general overview of the AMD-K6-2E+ processor's x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the AMD-K6-2E+ processor architecture and design implementation. The AMD-K6-2E+ processor implements the same ten ModelSpecific Registers (MSRs) as the AMD-K6-2 and AMD-K6-2E processors Model 8/[F:8], and the bits and fields within these ten MSRs are defined identically. The AMD-K6-2E+ processor supports an additional MSR for cache control. The low-power versions of the AMD-K6-2E+ processor support a twelfth MSR to control the AMD PowerNow! technology functions. See "Model-Specific Registers (MSR)" on page 44 for the MSR definitions. The model number for the AMD-K6-2E+ processor is Model D/[7:4], where the actual stepping can be any value in the range [7:4]. 3.1 Registers The AMD-K6-2E+ processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, MMX/3DNow!, EFLAGS, control, task, debug, test, and descriptor/memory-management registers. In addition, this chapter provides information on the AMD-K6-2E+ processor MSRs. Note: Areas of the register designated as Reserved should not be modified by software. Chapter 3 Software Environment 27