AMD AMD-K6-2/400 User Guide - Page 116

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.2 A20M# (Address Bit 20 Mask) Pin Attribute Input Summary A20M# is used to simulate the behavior of the 8086 when running in Real mode. The assertion of A20M # causes the processor to force bit 20 of the physical address to 0 prior to accessing the caches or driving out a memory bus cycle. The clearing of address bit 20 maps addresses that extend above the 8086 1-Mbyte limit to below 1 Mbyte. Sampled The processor samples A20M # as a level-sensitive input on every clock edge. The system logic can drive the signal either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. The following list explains the effects of the processor sampling A20M # asserted under various conditions: s Inquire cycles and writeback cycles are not affected by the state of A20M#. s The assertion of A20M# in System Management Mode (SMM) is ignored. s When A20M# is sampled asserted in Protected mode, it causes unpredictable processor operation. A20M# is only defined in Real mode. s To ensure that A20M# is recognized before the first ADS# occurs following the negation of RESET, A20M# must be sampled asserted on the same clock edge that RESET is sampled negated or on one of the two subsequent clock edges. s To ensure A20M# is recognized before the execution of an instruction, a serializing instruction must be executed between the instruction that asserts A20M# and the targeted instruction. (A serializing instruction is an instruction inserted between operations to enforce program order. It forces the processor to finish all modifications to flags, registers, and memory before the next instruction is executed.) 94 Signal Descriptions Chapter 5