AMD AMD-K6-2/400 User Guide - Page 36

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 s Long decodes-x86 instructions less than or equal to 11 bytes in length s Vector decodes-complex x86 instructions Short and long decodes are processed completely within the decoders. Vector decodes are started by the decoders and then completed by fetched sequences from an on-chip ROM. After decoding, the RISC86 operations are delivered to the scheduler for dispatching to the executions units. Scheduler/Instruction Control Unit The centralized scheduler or buffer is managed by the Instruction Control Unit (ICU). The ICU buffers and manages up to 24 RISC86 operations at a time. This equals from 6 to 12 x86 instructions. This buffer size (24) is perfectly matched to t h e p ro c e s s o r 's s i x -s t a g e R I S C 8 6 p i p e l i n e a n d f o u r RISC86-operations decode rate. The scheduler accepts as many as four RISC86 operations at a time from the decoders and retires up to four RISC86 operations per clock cycle. The ICU is capable of simultaneously issuing up to six RISC86 operations at a time to the execution units. This consists of the following types of operations: s Memory load operation s Memory store operation s Complex integer, MMX or 3DNow! register operation s Simple integer, MMX or 3DNow! register operation s Floating-point register operation s Branch condition evaluation Registers When managing the RISC86 operations, the ICU uses 69 physical registers contained within the RISC86 microarchitecture. s Forty-eight of the physical registers are located in a general register file. • Twenty-four of these are rename registers. • The other twenty-four are committed or architectural registers, consisting of 16 scratch registers and 8 registers that correspond to the x86 general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. 14 Internal Architecture Chapter 2