AMD AMD-K6-2/400 User Guide - Page 265
SMM StateSave Area, System Management Mode SMM
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 45 shows the initial state of registers when entering SMM. Table 45. Initial State of Registers in SMM Registers General Purpose Registers EFLAGS CR0 DR7 GDTR, LDTR, IDTR, TSSR, DR6 EIP CS DS, ES, FS, GS, SS SMM Initial State unmodified 0000_0002h PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31). The other bits are unmodified. 0000_0400h unmodified 0000_8000h 0003_0000h 0000_0000h 12.2 SMM State-Save Area When the processor acknowledges an SMI# interrupt by asserting SMIACT#, it saves its state in a 512-byte SMM state-save area shown in Table 46. The save begins at the top of the SMM memory area (SMM base address + FFFFh) and fills down to SMM base address + FE00h. Table 46 shows the offsets in the SMM state-save area relative to the SMM base address. The SMM service routine can alter any of the read/write values in the state-save area. Table 46. SMM State-Save Area Map Address Offset FFFCh FFF8h FFF4h FFF0h FFECh FFE8h FFE4h FFE0h FFDCh FFD8h FFD4h FFD0h Contents Saved CR0 CR3 EFLAGS EIP EDI ESI EBP ESP EBX EDX ECX EAX Chapter 12 System Management Mode (SMM) 243