AMD AMD-K6-2/400 User Guide - Page 227

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 9 Cache Organization The following sections describe the basic architecture and resources of the AMD-K6-2E+ processor internal caches. The performance of the AMD-K6-2E+ processor is enhanced by writeback level-one (L1) and level-two (L2) caches. s The L1 cache is organized as separate 32-Kbyte instruction and data caches, each with two-way set associativity. s The L2 cache is 128 Kbytes, and is organized as a unified, four-way set-associative cache (See Figure 82 on page 206). The cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. As the L1 instruction cache is filled from the L2 cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecode logic. Predecoding annotates each instruction byte in the L1 instruction cache with information that later enables the decoders to efficiently decode multiple instructions simultaneously. Translation lookaside buffers (TLB) are used in conjunction with the L1 cache to translate linear addresses to physical addresses. The L1 instruction cache is associated with a 64-entry TLB, while the L1 data cache is associated with a 128-entry TLB. Chapter 9 Cache Organization 205