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AMD AMD-K6-2/400 User Guide - Page 96

OR AL, imm8, OR EAX, imm16/32

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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Table 12. Integer Instructions (continued) Instruction Mnemonic OR reg16/32, mreg16/32 OR reg16/32, mem16/32 OR AL, imm8 OR EAX, imm16/32 OR mreg8, imm8 OR mem8, imm8 OR mreg16/32, imm16/32 OR mem16/32, imm16/32 OR mreg16/32, imm8 (signed ext.) OR mem16/32, imm8 (signed ext.) OUT imm8, AL OUT imm8, AX OUT imm8, EAX OUT DX, AL OUT DX, AX OUT DX, EAX POP ES POP SS POP DS POP FS POP GS POP EAX POP ECX POP EDX POP EBX POP ESP POP EBP POP ESI POP EDI POP mreg 16/32 POP mem 16/32 POPA/POPAD POPF/POPFD PUSH ES PUSH CS First Second Byte Byte 0Bh 0Bh 0Ch 0Dh 80h 80h 81h 81h 83h 83h E6h E7h E7h EEh EFh EFh 07h 17h 1Fh 0Fh A1h 0Fh A9h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 8Fh 8Fh 61h 9Dh 06h 0Eh ModR/M Byte 11-xxx-xxx mm-xxx-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-001-xxx mm-001-xxx 11-000-xxx mm-000-xxx Decode Type short short short short short long short long short long vector vector vector vector vector vector vector vector vector vector vector short short short short short short short short short long vector vector long vector RISC86 Operations alu load, alu alux alu alux load, alux, store alu load, alu, store alux load, alux, store load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, alu load, store, alu load, store 74 Software Environment Chapter 3

Section	Page
IF YOU HAVE QUESTIONS, WE\	3
Contents	5
List of Figures	9
List of Tables	13
Revision History	17
About this Data Sheet	19
1 AMDK6™2E+ Embedded Processor	23
1.1 AMDK6™2E+ Embedded Processor Features	25
1.2 Process Technology	29
1.3 Super7™ Platform	30
2 Internal Architecture	33
2.1 Microarchitecture Overview	33
2.2 Cache, Instruction Prefetch, and Predecode Bits	38
2.3 Instruction Fetch and Decode	39
2.4 Centralized Scheduler	43
2.5 Execution Units	44
2.6 BranchPrediction Logic	47
3 Software Environment	49
3.1 Registers	49
3.2 ModelSpecific Registers (MSR)	66
3.3 Memory Management Registers	76
3.4 Paging	78
3.5 Descriptors and Gates	81
3.6 Exceptions and Interrupts	84
3.7 Instructions Supported by the AMDK6™2E+ Processor	85
4 Logic Symbol Diagram	113
5 Signal Descriptions	115
5.1 Signal Terminology	115
5.2 A20M# (Address Bit 20 Mask)	116
5.3 A[31:3] (Address Bus)	117
5.4 ADS# (Address Strobe)	118
5.5 ADSC# (Address Strobe Copy)	118
5.6 AHOLD (Address Hold)	119
5.7 AP (Address Parity)	120
5.8 APCHK# (Address Parity Check)	121
5.9 BE[7:0]# (Byte Enables)	122
5.10 BF[2:0] (Bus Frequency)	123
5.11 BOFF# (Backoff)	124
5.12 BRDY# (Burst Ready)	125
5.13 BRDYC# (Burst Ready Copy)	126
5.14 BREQ (Bus Request)	126
5.15 CACHE# (Cacheable Access)	127
5.16 CLK (Clock)	127
5.17 D/C# (Data/Code)	128
5.18 D[63:0] (Data Bus)	129
5.19 DP[7:0] (Data Parity)	130
5.20 EADS# (External Address Strobe)	131
5.21 EWBE# (External Write Buffer Empty)	132
5.22 FERR# (FloatingPoint Error)	133
5.23 FLUSH# (Cache Flush)	134
5.24 HIT# (Inquire Cycle Hit)	135
5.25 HITM# (Inquire Cycle Hit To Modified Line)	135
5.26 HLDA (Hold Acknowledge)	136
5.27 HOLD (Bus Hold Request)	137
5.28 IGNNE# (Ignore Numeric Exception)	138
5.29 INIT (Initialization)	139
5.30 INTR (Maskable Interrupt)	140
5.31 INV (Invalidation Request)	140
5.32 KEN# (Cache Enable)	141
5.33 LOCK# (Bus Lock)	142
5.34 M/IO# (Memory or I/O)	143
5.35 NA# (Next Address)	144
5.36 NMI (NonMaskable Interrupt)	145
5.37 PCD (Page Cache Disable)	146
5.38 PCHK# (Parity Check)	147
5.39 PWT (Page Writethrough)	148
5.40 RESET (Reset)	149
5.41 RSVD (Reserved)	150
5.42 SCYC (Split Cycle)	151
5.43 SMI# (System Management Interrupt)	152
5.44 SMIACT# (System Management Interrupt Active)	153
5.45 STPCLK# (Stop Clock)	154
5.46 TCK (Test Clock)	155
5.47 TDI (Test Data Input)	155
5.48 TDO (Test Data Output)	155
5.49 TMS (Test Mode Select)	156
5.50 TRST# (Test Reset)	156
5.51 VCC2DET (VCC2 Detect)	157
5.52 VCC2H/L# (VCC2 High/Low)	158
5.53 VID[4:0] (Voltage Identification)	159
5.54 W/R# (Write/Read)	160
5.55 WB/WT# (Writeback or Writethrough)	161
5.56 Pin Tables by Type	162
5.57 Bus Cycle Definitions	164
6 AMD PowerNow!™ Technology	165
6.1 Enhanced Power Management Features	165
6.2 Dynamic Core Frequency and Core Voltage Control	172
7 Bus Cycles	175
7.1 Timing Diagrams	175
7.2 Bus States	177
7.3 Memory Reads and Writes	180
7.4 I/O Read and Write	188
7.5 Inquire and Bus Arbitration Cycles	190
7.6 Special Bus Cycles	212
8 Poweron Configuration and Initialization	221
8.1 Signals Sampled During the Falling Transition of RESET	221
8.2 RESET Requirements	222
8.3 State of Processor After RESET	222
8.4 State of Processor After INIT	225
9 Cache Organization	227
9.1 MESI States in the L1 Data Cache and L2 Cache	229
9.2 Predecode Bits	230
9.3 Cache Operation	230
9.4 Cache Disabling and Flushing	233
9.5 L2 Cache Testing	235
9.6 CacheLine Fills	235
9.7 CacheLine Replacements	236
9.8 Write Allocate	237
9.9 Prefetching	242
9.10 Cache States	243
9.11 Cache Coherency	244
9.12 Writethrough and Writeback Coherency States	249
9.13 A20M# Masking of Cache Accesses	249
10 Write Merge Buffer	251
10.1 EWBE# Control	251
10.2 Memory Type Range Registers	253
10.3 Memory-Range Restrictions	255
10.4 Examples	257
11 FloatingPoint and Multimedia Execution Units	259
11.1 FloatingPoint Execution Unit	259
11.2 Multimedia and 3DNow!™ Execution Units	261
11.3 FloatingPoint and MMX™/3DNow!™ Instruction Compatibility	262
12 System Management Mode (SMM)	263
12.1 SMM Operating Mode and Default Register Values	263
12.2 SMM StateSave Area	265
12.3 SMM Revision Identifier	267
12.4 SMM Base Address	268
12.5 Halt Restart Slot	268
12.6 I/O Trap Doubleword	269
12.7 I/O Trap Restart Slot	270
12.8 Exceptions, Interrupts, and Debug in SMM	272
13 Test and Debug	273
13.1 BuiltIn SelfTest (BIST)	273
13.2 ThreeState Test Mode	274
13.3 BoundaryScan Test Access Port (TAP)	275
13.4 Cache Inhibit	285
13.5 L2 Cache and Tag Array Testing	286
13.6 Debug	290
14 Clock Control	297
14.1 Clock Control States	297
14.2 Halt State	300
14.3 Stop Grant State	300
14.4 Stop Grant Inquire State	302
14.5 EPM Stop Grant State	303
14.6 Stop Clock State	305
15 Electrical Data	307
15.1 Operating Ranges	308
15.2 Absolute Ratings	309
15.3 DC Characteristics	309
15.4 Power Dissipation	311
15.5 Power and Grounding	313
16 Signal Switching Characteristics	317
16.1 CLK Switching Characteristics	318
16.2 Clock Switching Characteristics for 100MHz Bus Operation	318
16.3 Clock Switching Characteristics for 66MHz Bus Operation	319
16.4 Valid Delay, Float, Setup, and Hold Timings	320
16.5 Output Delay Timings for 100MHz Bus Operation	320
16.6 Input Setup and Hold Timings for 100MHz Bus Operation	322
16.7 Output Delay Timings for 66MHz Bus Operation	324
16.8 Input Setup and Hold Timings for 66MHz Bus Operation	326
16.9 RESET and Test Signal Timing	328
16.10 Timing Diagrams	331
17 Thermal Design	335
17.1 Package Thermal Specifications	335
17.2 Measuring Case Temperature	339
17.3 Layout and Airflow Considerations	339
18 Pin Designations	343
18.1 Pins Designations for CPGA Package	344
18.2 Pins Designations for OBGA Package	348
19 Package Specifications	353
19.1 321Pin Staggered CPGA Package Specification	353
19.2 349Ball OBGA Package Specification	354
20 Ordering Information	355

Match case Limit results 1 per page

Software Environment

Chapter 3

AMD-K6™-2E+ Embedded Processor Data Sheet

23542A/0—September 2000

Preliminary Information

OR reg16/32, mreg16/32

0Bh

11-xxx-xxx

short

alu

OR reg16/32, mem16/32

0Bh

mm-xxx-xxx

short

load, alu

OR AL, imm8

0Ch

short

alux

OR EAX, imm16/32

0Dh

short

alu

OR mreg8, imm8

80h

11-001-xxx

short

alux

OR mem8, imm8

80h

mm-001-xxx

long

load, alux, store

OR mreg16/32, imm16/32

81h

11-001-xxx

short

alu

OR mem16/32, imm16/32

81h

mm-001-xxx

long

load, alu, store

OR mreg16/32, imm8 (signed ext.)

83h

11-001-xxx

short

alux

OR mem16/32, imm8 (signed ext.)

83h

mm-001-xxx

long

load, alux, store

OUT imm8, AL

E6h

vector

OUT imm8, AX

E7h

vector

OUT imm8, EAX

E7h

vector

OUT DX, AL

EEh

vector

OUT DX, AX

EFh

vector

OUT DX, EAX

EFh

vector

POP ES

07h

vector

POP SS

17h

vector

POP DS

1Fh

vector

POP FS

0Fh

A1h

vector

POP GS

0Fh

A9h

vector

POP EAX

58h

short

load, alu

POP ECX

59h

short

load, alu

POP EDX

5Ah

short

load, alu

POP EBX

5Bh

short

load, alu

POP ESP

5Ch

short

load, alu

POP EBP

5Dh

short

load, alu

POP ESI

5Eh

short

load, alu

POP EDI

5Fh

short

load, alu

POP mreg 16/32

8Fh

11-000-xxx

short

load, alu

POP mem 16/32

8Fh

mm-000-xxx

long

load, store, alu

POPA/POPAD

61h

vector

POPF/POPFD

9Dh

vector

PUSH ES

06h

long

load, store

PUSH CS

0Eh

vector

Table 12.

Integer Instructions (continued)

Instruction Mnemonic

First

Byte

Second

Byte

ModR/M

Byte

Decode

Type

RISC86

Operations