AMD AMD-K6-2/400 User Guide - Page 255

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 10.3 WCn (n=0, 1). When set to 1, this memory range is defined as write combinable (see Table 43). Write-combinable memory is uncacheable. UCn (n=0, 1). When set to 1, this memory range is defined as uncacheable (see Table 43). Table 43. WC/UC Memory Type WCn 0 1 0 or 1 UCn Memory Type 0 No effect on cacheability or write combining 0 Write-combining memory range (uncacheable) 1 Uncacheable memory range Memory-Range Restrictions The following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the UWCCR register: s The minimum size of each range is 128 Kbytes. s The physical base address must be aligned on a 128-Kbyte boundary. s The physical base address must be range-size aligned. For example, if the size of the range is 1 Mbyte, then the physical base address must be aligned on a 1-Mbyte boundary. s All bits set to 1 in the physical address mask must be contiguous. Likewise, all bits set to 0 in the physical address mask must be contiguous. For example: 111_1111_1100_0000b is a valid physical address mask. 111_1111_1101_0000b is invalid. Chapter 10 Write Merge Buffer 233