AMD AMD-K6-2/400 User Guide - Page 289

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet as illustrated in Figure 94. Similarly, if the L2 cache data is written, the write data is taken from EAX. 31 0 Data Figure 94. L2 Data - EAX L2 Tag Reads 31 If the L2 tag is read (as opposed to reading the cache data), the result is placed in EAX in the format as illustrated in Figure 95 on page 267. Similarly, if the L2 tag is written, the write data is taken from EAX. When accessing the L2 tag, the Line, Octet, and Dword fields of the EDX register are ignored. . 14 13 12 11 10 9 8 7 0 C Tag Line1ST Line0ST LRU M D Reserved Symbol Description Bit Tag Tag data read or written 31-14 Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10 Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8 LRU Two bits of LRU for each way 7-0 Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor-EAX LRU (Least Recently Used). For the 4-way set associative L2 cache, each way has a 2-bit LRU field for each sector. Values for the LRU field are 00b, 01b, 10b, and 11b, where 00b indicates that the sector is "most recently used," and 11b indicates that the sector is "least recently used" (see Figure 96 on page 268). EAX[7:6] indicate LRU information for Way 0, EAX[5:4] for Way 1, EAX[3:2] for Way 2, and EAX[1:0] for Way 3. Chapter 13 Test and Debug 267