AMD AMD-K6-2/400 User Guide - Page 20
System Management Mode SMM on Power-on Configuration and Initialization - processor multimedia technology
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Chapter 8, "Power-on Configuration and Initialization" on page 199, describes how the system logic resets the AMD-K6-2E+ processor using the RESET signal. Chapter 9, "Cache Organization" on page 205, describes the b a si c a rch it e c t ure a n d re s o u rc e s o f t h e A M D -K 6 -2 E+ processor's internal caches. Chapter 10, "Write Merge Buffer" on page 229, describes the 8byte write merge buffer and how merging multiple write cycles into a single write cycle ultimately increases overall system performance. Chapter 11, "Floating-Point and Multimedia Execution Units" on page 237, describes the AMD-K6-2E+ processor's IEEE 754compatible and 854-compatible floating point execution unit, the multimedia and 3DNow!™ technology execution units, and the floating-point and MMX™/3DNow! technology instruction compatibility. Chapter 12, "System Management Mode (SMM)" on page 241, describes SMM, the state-save area, entry into and exit from SMM, exceptions and interrupts in SMM, memory allocation and addressing in SMM, and the SMI# and SMIACT# signals. Chapter 13, "Test and Debug" on page 251, describes the various test and debug modes that enable the functional and manufacturing testing of systems and boards that use the AMD-K6-2E+ processor and that allow designers to debug the instruction execution of software components. Chapter 14, "Clock Control" on page 275, describes the five modes of clock control supported by the AMD-K6-2E+ processor. Chapter 15, "Electrical Data" on page 285, includes operating ranges, absolute ratings, DC characteristics, power dissipation data, power and grounding information, and decoupling recommendations. Chapter 16, "Signal Switching Characteristics" on page 295, provides tables listing valid delay, float, setup, and hold timing specifications for the AMD-K6-2E+ processor signals. xx About this Data Sheet