AMD AMD-K6-2/400 User Guide - Page 273
Test and Debug, 13.1 BuiltIn SelfTest (BIST)
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 13 13.1 Test and Debug The AMD-K6-2E+ processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. In addition, the debug features of the processor allow designers to debug the instruction execution of software components. This chapter describes the following test and debug features: s Built-In Self-Test (BIST)-The BIST, which is invoked after the falling transition of RESET, runs internal tests that exercise most on-chip RAM structures. s Three-State Test Mode-A test mode that causes the processor to float its output and bidirectional pins. s Boundary-Scan Test Access Port (TAP) -The Joint Test Action Group (JTAG) test access function defined by the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-1990) specification. s Cache Inhibit-A feature that disables the processor's internal L1 and L2 caches. s Level-2 Cache Array Access Register (L2AAR)-The AMD-K6-2E+ processor provides the L2AAR that allows for direct access to the L2 cache and L2 tag arrays. s Debug Support-Consists of all x86-compatible software debug features, including the debug extensions. Built-In Self-Test (BIST) Following the falling transition of RESET, the processor unconditionally runs its built-in self test (BIST). The internal resources tested during BIST include the following: s L1 instruction and data caches s L2 cache s Instruction and Data Translation Lookaside Buffers (TLBs) Chapter 13 Test and Debug 251