AMD AMD-K6-2/400 User Guide - Page 328

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.9 RESET and Test Signal Timing Table 68. RESET and Configuration Signals for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure t90 RESET Setup Time 1.7 ns 109 t91 RESET Hold Time 1.0 ns 109 t92 RESET Pulse Width, VCC and CLK Stable 15 clocks 109 t93 RESET Active After VCC and CLK Stable 1.0 ms 109 t941 BF[2:0] Setup Time 1.0 ms 109 t951 BF[2:0] Hold Time 2 clocks 109 t96 Intentionally left blank t97 Intentionally left blank t98 Intentionally left blank t992 FLUSH# Setup Time 1.7 ns 109 t1002 FLUSH# Hold Time 1.0 ns 109 t1013 FLUSH# Setup Time 2 clocks 109 t1023 FLUSH# Hold Time 2 clocks 109 Notes: 1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET. 2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET is sampled negated. 3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of RESET. 306 Signal Switching Characteristics Chapter 16