AMD AMD-K6-2/400 User Guide - Page 11
Stop Grant and Stop Clock Modes, Part 1 .194, INIT-Initiated Transition from Protected Mode to Real - 266
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet List of Figures Figure 73. BOFF# Timing 183 Figure 74. Basic Locked Operation 185 Figure 75. Locked Operation with BOFF# Intervention 187 Figure 76. Interrupt Acknowledge Operation 189 Figure 77. Basic Special Bus Cycle (Halt Cycle 191 Figure 78. Shutdown Cycle 192 Figure 79. Stop Grant and Stop Clock Modes, Part 1 194 Figure 80. Stop Grant and Stop Clock Modes, Part 2 195 Figure 81. INIT-Initiated Transition from Protected Mode to Real Mode 197 Figure 82. L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor 206 Figure 83. L1 Cache Sector Organization 207 Figure 84. Write Handling Control Register (WHCR 217 Figure 85. Write Allocate Logic Mechanisms and Conditions 218 Figure 86. Page Flush/Invalidate Register (PFIR 224 Figure 87. UC/WC Cacheability Control Register (UWCCR 232 Figure 88. External Logic for Supporting Floating-Point Exceptions. . . 239 Figure 89. SMM Memory 242 Figure 90. TAP State Diagram 261 Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor 265 Figure 92. L2 Cache Sector and Line Organization 265 Figure 93. L2 Tag or Data Location for the AMD-K6™-2E+ Processor-EDX 266 Figure 94. L2 Data - EAX 267 Figure 95. L2 Tag Information for the AMD-K6™-2E+ Processor-EAX 267 Figure 96. LRU Byte 268 Figure 97. Debug Register DR7 269 Figure 98. Debug Register DR6 270 Figure 99. Debug Registers DR5 and DR4 270 Figure 100. Debug Registers DR3, DR2, DR1, and DR0 271 Figure 101. Clock Control State Transitions for Standard-Power Versions of the AMD-K6™-2E+ Processor 276 Figure 102. Clock Control State Transitions for Low-Power Versions of the AMD-K6™-2E+ Processor 277 Figure 103. Suggested Component Placement for CPGA Package 292 Figure 104. CLK Waveform 297 Figure 105. Key to Timing Diagrams 309 xi