AMD AMD-K6-2/400 User Guide - Page 67
Machine Check, Address Register, MCAR and Machine, Check Type Register,
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Machine Check Address Register (MCAR) and Machine Check Type Register (MCTR) 63 The AMD-K6-2E+ processor does not support the generation of a machine check exception. However, the processor does provide a 64-bit machine check address register (MCAR), a 64-bit machine check type register (MCTR), and a machine check enable (MCE) bit in CR4. Because the processor does not support machine check exceptions, the contents of the MCAR and MCTR are only affected by the WRMSR instruction and by RESET being sampled asserted (where all bits in each register are reset to 0). The formats for the machine-check address register and the machine-check type register are shown in Figure 30 and Figure 31, respectively. The MCAR register is MSR 00h, and the MCTR register is MSR 01h. 0 MCAR Figure 30. Machine-Check Address Register (MCAR) 63 Reserved Figure 31. Machine-Check Type Register (MCTR) 54 0 MCTR Chapter 3 Software Environment 45