AMD AMD-K6-2/400 User Guide - Page 318

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 16.1 CLK Switching Characteristics Table 62 and Table 63 on page 297 contain the switching characteristics of the CLK input to the AMD-K6-2E+ processor for 100-MHz and 66-MHz bus operation, respectively, as measured at the voltage levels indicated by Figure 104 on page 297. The CLK Period Stability parameter specifies the variance (jitter) allowed between successive periods of the CLK input measured at 1.5 V. This parameter must be considered as one of the elements of clock skew between the AMD-K6-2E+ processor and the system logic. 16.2 Clock Switching Characteristics for 100-MHz Bus Operation Table 62. CLK Switching Characteristics for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments Frequency t1 CLK Period t2 CLK High Time t3 CLK Low Time t4 CLK Fall Time t5 CLK Rise Time CLK Period Stability1 33.3 MHz 10.0 ns 3.0 ns 3.0 ns 0.15 ns 0.15 ns 100 MHz 1.5 ns 1.5 ns – 250 ps In Normal Mode 104 In Normal Mode 104 104 104 104 Notes: 1. The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz. 296 Signal Switching Characteristics Chapter 16