AMD AMD-K6-2/400 User Guide - Page 69
Extended Feature, Enable Register, Extended Feature Enable Register EFER, Table 6.
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Extended Feature Enable Register (EFER) 63 The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the processor. Figure 34 shows the format of the EFER register, and Table 6 defines the function of each bit of the EFER register. The EFER register is MSR C000_0080h. 54 3 2 1 0 L DS 2 EWBEC P C D EE Reserved Symbol Description Bit L2D L2 Cache Disable 4 EWBEC EWBE# Control 3-2 DPE Data Prefetch Enable 1 SCE System Call Extension 0 Figure 34. Extended Feature Enable Register (EFER) Table 6. Extended Feature Enable Register (EFER) Definition Bit Description 63-5 Reserved 4 L2D 3-2 EWBE Control (EWBEC) 1 Data Prefetch Enable (DPE) 0 System Call Extension (SCE) R/W Function R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for debug and R/W testing purposes. For normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). This 2-bit field controls the behavior of the processor with respect to the ordering of write R/W cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE Disable (GEWBED) and Speculative EWBE Disable (SEWBED), respectively. DPE must be set to 1 to enable data prefetching (this is the default setting following R/W reset). If enabled, cache misses initiated by a memory read within a 32-byte line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. For more information about the EWBEC bits, see "EWBE# Control" on page 229. Chapter 3 Software Environment 47