AMD AMD-K6-2/400 User Guide - Page 285
Cache Inhibit, The following states have no effect on the normal or test
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 13.4 The following states have no effect on the normal or test operation of the processor other than as shown in Figure 90 on page 261: s Run-Test/Idle-This state is an idle state between scan operations. s Select-DR-Scan-This is the initial state of the test data register state transitions. s Select-IR-Scan-This is the initial state of the Instruction Register state transitions. s Exit1-DR-This state is entered to terminate the shifting process and enter the Update-DR state. s Exit1-IR-This state is entered to terminate the shifting process and enter the Update-IR state. s Pause-DR-This state is entered to temporarily stop the shifting process of a Test Data Register. s Pause-IR-This state is entered to temporarily stop the shifting process of the Instruction Register. s Exit2-DR-This state is entered in order to either terminate the shifting process and enter the Update-DR state or to resume shifting following the exit from the Pause-DR state. s Exit2-IR-This state is entered in order to either terminate the shifting process and enter the Update-IR state or to resume shifting following the exit from the Pause-IR state. Cache Inhibit The AMD-K6-2E+ processor provides a means for inhibiting the normal operation of its internal L1 and L2 caches while still supporting an external cache. This capability allows system designers to disable the L1 and L2 caches during the testing and debug of an L3 cache. If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set to 0, the processor's L1 and L2 caches are enabled and operate as described in "Cache Organization" on page 205. If the Cache Inhibit bit is set to 1, the L1 and L2 caches are disabled and no new cache lines are allocated. Even though new allocations do not occur, valid L1 and L2 cache lines remain valid and are read by the processor when a requested address hits a cache line. In addition, the processor continues to support inquire cycles Chapter 13 Test and Debug 263