AMD AMD-K6-2/400 User Guide - Page 240

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Sector" mechanisms). The WAE15M bit is ignored if the value in the WAELIM field is set to less than 16 Mbytes. By definition a write allocate is not performed in the memory area between 640 Kbytes and 1 Mbyte unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanisms-"Write to a Cacheable Page" and "Write to a Sector." It is not considered safe to perform write allocations between 640 Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered a noncacheable region of memory. If a memory region is defined as write combinable or uncacheable by a MTRR, write allocates are not performed in that region. Write Allocate Logic Mechanisms and Conditions Figure 85 shows the logic flow for all the mechanisms involved with write allocate for memory bus cycles. The left side of the diagram (the text) describes the conditions that need to be true in order for the value of that line to be a 1. Items 1 to 4 of the diagram are related to general cache operation and items 5 to 10 are related to the write allocate mechanisms. For more information about write allocate, see the Implementation of Write Allocate in the K86™ Processors Application Note, order# 21326. 1) CD Bit of CR0 2) PCD Signal 3) CI Bit of TR12 4) UC or WC 5) Write to Cacheable Page (CCR) 6) Write to a Sector 7) Less Than Limit (WAELIM) 8) Between 640 Kbytes and 1 Mbyte 9) Between 15-16 Mbytes 10) Write Allocate Enable 15-16 Mbyte (WAE15M) Perform Write Allocate Figure 85. Write Allocate Logic Mechanisms and Conditions 218 Cache Organization Chapter 9