AMD AMD-K6-2/400 User Guide - Page 72

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 Page Flush/Invalidate Register (PFIR) 63 The AMD-K6-2E+ processor contains the Page Flush/Invalidate Register (PFIR) (see Figure 39) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. For more detailed information on PFIR, see "Page Flush/Invalidate Register (PFIR)" on page 223. The PFIR register is MSR C000_0088h. 32 31 12 11 9 8 7 10 LINPAGE P F F / I Symbol LINPAGE PF F/I Reserved Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command Bit 31-12 8 0 Figure 39. Page Flush/Invalidate Register (PFIR) Level-2 Cache Array Access Register (L2AAR) The AMD-K6-2E+ processor provides the L2AAR register that allows for direct access to the L2 cache and L2 tag arrays. The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the contents of the EDX register. The EDX register specifies the location of the access, and whether the access is to the L2 cache data or tags (refer to Figure 40). 50 Software Environment Chapter 3