AMD AMD-K6-2/400 User Guide - Page 287

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Set 0 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 512 sets Set 511 Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor Octet 0 Octet 1 Octet 2 Octet 3 Figure 92 shows the L2 cache sector and line organization. If bit 5 of the address of a cache line equals 1, then this cache line is stored in Line 1 of a sector. Similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in Line 0 of a sector. Upper Dword Lower Dword Upper Dword Lower Dword Line 1 Figure 92. L2 Cache Sector and Line Organization Sector Line 0 The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the contents of the EDX register. The EDX register specifies the location of the access, and whether the access is to the L2 cache data or tags (refer to Figure 93 on page 266). Bit 20 of EDX (T/D) determines whether the access is to the L2 cache data or tag. Table 53 on Chapter 13 Test and Debug 265