AMD AMD-K6-2/400 User Guide - Page 243

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 9.10 Cache States Table 39 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. Table 39. L1 and L2 Cache States for Read and Write Accesses Cache State Before Access1 Type Access Type Cache State After Access MESI State2 Read Miss L1, Read Miss L2 Read Hit L1 Cache Read Read Miss L1, Read Hit L2 Write Miss L1 Write Miss L2 Write Hit L1 Cache Write Write Miss L1 Write Hit L2 L1 I I E S M I I I I I I I S S E or M I I I I I I L2 L1 I Single read from bus I I Burst read from bus, fill L1 and L23 S or E4 - - E - - S - - M E Fill L1 E S Fill L1 S M Fill L1 M M Fill L1 E5 I Single write to bus6 I I Burst read from bus, fill L1 and L2, write to L17 M8 Burst read from bus, fill L1 and L2, write to I L1 and L2, single write to bus7 S9 I Write to L1, single write to bus S or E4 S Write to L1 and L2, single write to bus S or E4 - Write to L1 M E Write to L26 I S Write to L2, single write to bus6 I M Write to L26 I E Fill L1, write to L17 M S Write to L2, single write to bus7 S or E4 M Fill L1, write to L17 M L2 I S or E4 - - - E S E M5 I E8 S9 I S or E4 - M S or E4 M E S or E4 E Notes: 1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the L1 instruction cache and are treated as "valid" states. 2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line. 3. If CACHE# is driven Low and KEN# is sampled asserted. 4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or WB/WT# is sampled Low, the line is cached in the shared (writethrough) state. Chapter 9 Cache Organization 221