AMD AMD-K6-2/400 User Guide - Page 122

Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 5.9 BE[7:0]# (Byte Enables) Pin Attribute Output Summary BE[7:0]# are used by the processor to indicate the valid data bytes during a write cycle and the requested data bytes during a read cycle. The byte enables can be used to derive address bits A[2:0], which are not physically part of the processor's address bus. The processor checks and generates valid data parity for the data bytes that are valid as defined by the byte enables. The eight byte enables correspond to the eight bytes of the data bus as follows: s BE7#: D[63:56] s BE6#: D[55:48] s BE5#: D[47:40] s BE4#: D[39:32] s BE3#: D[31:24] s BE2#: D[23:16] s BE1#: D[15:8] s BE0#: D[7:0] The processor expects data to be driven by the system logic on all eight bytes of the data bus during a burst cache-line read cycle, independent of the byte enables that are asserted. The byte enables are also used to distinguish between special bus cycles as defined in Table 24 on page 142. Driven and Floated BE[7:0]# are driven off the same clock edge as ADS # and remain in the same state until the clock edge on which NA# or the last expected BRDY # of the cycle is sampled asserted. BE[7:0]# are driven during memory cycles, I/O cycles, special bus cycles, and interrupt acknowledge cycles. The processor floats BE[7:0]# off the clock edge that BOFF# is sampled asserted and off the clock edge that the processor asserts HLDA in recognition of HOLD. Unlike the address bus, BE[7:0]# are not floated in response to AHOLD. 100 Signal Descriptions Chapter 5