AMD AMD-K6-2/400 User Guide - Page 323

23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 65. Input Setup and Hold Timings for 100-MHz Bus Operation (continued) Symbol Parameter Description Preliminary Data Min Max Figure t732 INIT Hold Time 1.0 ns 108 t741 INTR Setup Time t751 INTR Hold Time t76 INV Setup Time t77 INV Hold Time t78 KEN# Setup Time t79 KEN# Hold Time t80 NA# Setup Time t81 NA# Hold Time t822 NMI Setup Time t832 NMI Hold Time 1.7 ns 108 1.0 ns 108 1.7 ns 108 1.0 ns 108 3.0 ns 108 1.0 ns 108 1.7 ns 108 1.0 ns 108 1.7 ns 108 1.0 ns 108 t842 SMI# Setup Time 1.7 ns 108 t852 SMI# Hold Time 1.0 ns 108 t861 STPCLK# Setup Time t871 STPCLK# Hold Time t88 WB/WT# Setup Time t89 WB/WT# Hold Time 1.7 ns 108 1.0 ns 108 1.7 ns 108 1.0 ns 108 Notes: 1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks. 2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain asserted at least two clocks. Chapter 16 Signal Switching Characteristics 301