AMD AMD-K6-2/400 User Guide - Page 228
L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor, Cache Organization - ram
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 System Bus Interface Unit 32-Kbyte L1 Instruction Cache Tag Way 0 State Tag Way 1 State RAM Bit RAM Bit 64-Entry TLB Pre-Decode Instruction Cache 128-Entry TLB Tag Way 0 MESI Tag Way 1 MESI RAM Bits RAM Bits 32-Kbyte L1 Data Cache Processor Core Tag MESI Tag MESI Tag MESI Tag MESI RAM Way 0 Bits RAM Way 1 Bits RAM Way 2 Bits RAM Way 3 Bits 128-Kbyte L2 Cache Figure 82. L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor The processor cache design takes advantage of a sectored organization (See Figure 83). Each sector consists of 64 bytes configured as two 32-byte cache lines. The two cache lines of a sector share a common tag but have separate MESI (modified, exclusive, shared, invalid) bits that track the state of each cache line. 206 Cache Organization Chapter 9