AMD AMD-K6-2/400 User Guide - Page 35
Internal Architecture, Decoders
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet ÃHC Tr & 7 Dr shpr Q rqrpqr Gtvp "!ÃF7rÃGrryPrÃD pvÃ8hpur !ÃF7rÃQ rqrpqrÃ8hpur DUG7 GrryPrÃ8hpur 8 yyr PsP qr @rpvÃ@tvr TvÃSDT8'% Pr hvÃDr %Ã7rÃArpu 9hyÃD pvÃ9rpqr SDT8'% 7 hpuÃGtvp 7CU 7U8 S6T A ÃSDT8'% 9rpqr Tpurqyr 7ssr !#ÃSDT8'% D pv 8 yÃVv 7 hpu SryvÃVv GrryU 8hpur !'ÃF7r Ghq Vv T r Vv T r Rrr Srtvr ÃVvÃY Drtr 70 Hyvrqvh"9IÄ GrryPrÃ9hyQ Ã9hhÃ8hpur Ã"!ÃF7r 9UG7 Figure 1. AMD-K6™-2E+ Processor Block Diagram Srtvr ÃVvÃ` Drtr Hyvrqvh"9IÄ AyhvtÃQv Vv Decoders Chapter 2 Decoding of the x86 instructions begins when the on-chip L1 instruction cache is filled. Predecode logic determines the length of an x86 instruction on a byte-by-byte basis. This predecode information is stored, along with the x86 instructions, in the L1 instruction cache, to be used later by the decoders. The decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into RISC86 operations. Note: In this chapter, "clock" refers to a processor clock. The AMD-K6-2E+ processor categorizes x86 instructions into three types of decodes-short, long, and vector. The decoders process either two short, one long, or one vector decode at a time. The three types of decodes have the following characteristics: s Short decodes-x86 instructions less than or equal to seven bytes in length Internal Architecture 13