Intel VC820 Design Guide - Page 109
Monte Carlo Analysis, 3.2.3.4 Simulation Criteria, both fast and slow corner conditions
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Advanced System Bus Design 3.2.3.3 3.2.3.4 Monte Carlo Analysis Perform a Monte Carlo analysis to refine the passing solution space region. A Monte Carlo analysis involves randomly varying parameters (independent of one another) over their tolerance range. This analysis intends to ensure that no regions of failing flight time and signal quality exists between the extreme corner cases run in pre-layout simulations. For the example topology, vary the following parameters during Monte Carlo simulations: • Lengths L1 through L3 • Termination resistance RTT on the processor cartridge #1 • Termination resistance RTT on the processor cartridge #2 • Z0 of traces on processor cartridge #1 • Z0 of traces on processor cartridge #2 • S0 of traces on processor cartridge #1 • S0 of traces on processor cartridge #2 • Z0 of traces on baseboard • S0 of traces on baseboard • Fast and slow corner processor I/O buffer models for cartridge #1 • Fast and slow corner processor I/O buffer models for cartridge #2 • Fast and slow package models for processor cartridge #1 • Fast and slow package models for processor cartridge #2 • Fast and slow corner 82820 MCH I/O buffer models • Fast and slow 82820 MCH package models Simulation Criteria Accurate simulations require that the actual range of parameters be used in the simulations. Intel has consistently measured the cross-sectional resistivity of the PCB copper to be approximately 1 Ω*mil2/inch, not the 0.662 Ω*mil2/inch value for annealed copper that is published in reference material. Using the 1 Ω*mil2/inch value may increase the accuracy of lossy simulations. Positioning drivers with faster edges closer to the middle of the network typically results in more noise than positioning them towards the ends. However, Intel has shown that drivers located in all positions (given appropriate variations in the other network parameters) can generate the worstcase noise margin. Therefore, Intel recommends simulating the networks from all driver locations, and analyzing each receiver for each possible driver. Analysis has shown that both fast and slow corner conditions must be run for both rising and falling edge transitions. The fast corner is needed because the fast edge rate creates the most noise. The slow corner is needed because the buffer's drive capability will be a minimum, causing the VOL to shift up, which may cause the noise from the slower edge to exceed the available budget. Slow corner models may produce minimum flight time violations on rising edges if the transition starts from a higher VOL. So, Intel highly recommends checking for minimum and maximum flight time violations with both the fast and slow corner models. The fast and slow corner I/O buffer models are contained in the processor and Intel 820 chipset electronic models provided by Intel. The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. Editing the simulator's net description or topology file generally does this. Intel®820 Chipset Design Guide 3-9