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ICH_A, ICH

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8 ICH D 7 16,20,21 AD[31:0] C 16,20,21 C_BE#[3:0] 16,20,21,32 16,20,21,32 16,20,21,32 16,20,21,32 B 16,20,21,32 16,20,21 6,10,11,12,16,19,20,21,22 20,21,32 16,20,21,32 16,20,21,32 16,19,20,21 21,32 21,32 5 A 8 7 6 5 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3 DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PCIRST# PLOCK# SERR# PERR# PCI_PME# REQ#A GNT#A ICHPCLK U13 ICH_096 G2 AD0 G4 AD1 F2 AD2 F3 AD3 F4 AD4 F5 AD5 E1 AD6 E2 AD7 D1 AD8 D3 AD9 E4 AD10 C2 AD11 C1 AD12 B1 AD13' D4 AD14 C3 AD15 A4 AD16 B4 AD17 C5 AD18 C6 AD19 B5 AD20 E7 AD21 A6 AD22 B6 AD23 D7 AD24 B8 AD25 PCI A7 AD26 A8 AD27 B7 AD28 C9 AD29 D8 AD30 C7 AD31 D2 CBE0# B2 CBE#1 A3 CBE#2 D6 CBE#3 D9 DEVSEL# B3 FRAME# A2 IRDY# C4 TRDY# D5 STOP# A9 PAR J5 PCIRST# B9 PLOCK# A1 SERR# E9 PERR#/GPIO7 K1 PME# N6 GPIO0/REQ#A P5 GPIO16/GNT#A C14 PCICLK VCC1_8;G13,H14,K14,G15,L15,H16,J16 VCC3_3;C11,E13,N13,R13,M14,D16,T16 VCC3_3;E3,A5,E5,G5,N5,E6,P6,T7,C8,U10 GND;R2,G3,H8,J8,K8,H9,J9,K9,H10,J10,K10,G14,K15 4 3 2 1 CPU ICH_A HUB A20M# F13 CPUSLP# E12 FERR# F15 IGNNE# B17 INIT# E15 INTR E14 NMI B16 SMI# F14 STPCLK# A17 RCIN# A15 A20GATE B15 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HL_STB HL_STB# HLCOMP HUBREF D17 E17 F17 G16 J15 K16 K17 L17 H15 J17 J14 F16 G17 H17 M17 J13 PIRQA# D10 PIRQB# A10 PIRQC# B10 PIRQD# C10 IRQ IRQ14 P11 IRQ15 N14 APICCLK C16 APICD0 E16 APICD1 C17 SERIRQ R4 REQ#0 A14 REQ#1 B13 REQ#2 B12 REQ#3 D12 REQ#4 B11 PCI GPIO1/REQ#B/REQ#5 P4 GNT#0 A13 GNT#1 C13 GNT#2 A12 GNT#3 C12 GNT#4 A11 GPIO17/GNT#B/GNT#5 R5 A20M# SLP# FERR# IGNNE# HINIT# LINT0 LINT1 SMI# STPCLK# KBRST# A20GATE HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11_TP HL_STB HL_STB# ICH_HLCOMP PIRQ#A PIRQ#B PIRQ#C PIRQ#D IRQ14 IRQ15 APICCLK PICD0 PICD1 SERIRQ PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5 PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 PGNT#5 4,32 4,32 4,32 4,32 4,10,32 4,32 4,32 4,32 4,32 12,32 12,32 HL[10:0] D 7 Place R239 less than 0.5" from the ICH using a 10 mil trace. VCC1_8 R239 40.2-1% TP1 C 7,37 7,37 HUBREF 6,8,37 16,19,20,21,32 19,20,21,32 20,21,32 20,21,32 C237 0.01UF Place C237 close to ICH. 22,32 22,32 5 4,32 4,32 12,21,32 VCC1_8 B 20,32 R225 301-1% 20,32 21,32 16,32 32 21,32 6,8,37 HUBREF R226 301-1% 20,32 20,32 21,32 16,32 32 21,32 C218 0.1UF Place HUBREF circuit between MCH and ICH HUBREF voltage = 0.9V +/- 2% A TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: ICH 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-24-1999_11:14 8 OF 36 6 5 4 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-24-1999_11:14

ICH

6,8,37

HUBREF

PGNT#5

21,32

PGNT#4

PGNT#3

16,32

21,32

PGNT#2

PGNT#1

20,32

PGNT#0

20,32

PREQ#5

21,32

PREQ#4

PREQ#3

16,32

PREQ#2

21,32

PREQ#1

20,32

PREQ#0

12,21,32

SERIRQ

4,32

PICD1

PICD0

4,32

APICCLK

IRQ15

22,32

IRQ14

22,32

20,21,32

PIRQ#D

PIRQ#C

20,21,32

19,20,21,32

PIRQ#B

PIRQ#A

16,19,20,21,32

6,8,37

HUBREF

7,37

HL_STB#

HL[10:0]

HL10

HL9

HL8

HL7

HL6

HL5

HL4

HL3

HL2

HL1

HL0

AD[31:0]

16,20,21

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

16,20,21

C_BE#[3:0]

C_BE#0

C_BE#1

C_BE#2

C_BE#3

DEVSEL#

16,20,21,32

FRAME#

16,20,21,32

IRDY#

16,20,21,32

TRDY#

16,20,21,32

STOP#

16,20,21,32

PAR

16,20,21

PCIRST#

6,10,11,12,16,19,20,21,22

PLOCK#

20,21,32

SERR#

16,20,21,32

PERR#

16,20,21,32

16,19,20,21

PCI_PME#

ICHPCLK

12,32

A20GATE

12,32

KBRST#

STPCLK#

4,32

SMI#

4,32

LINT1

4,32

LINT0

HINIT#

4,10,32

IGNNE#

4,32

FERR#

4,32

SLP#

A20M#

4,32

R226

301-1%

R225

301-1%

40.2-1%

R239

21,32

REQ#A

21,32

GNT#A

ICH_HLCOMP

HL11_TP

U13

M17

H17

G17

J17

H15

L17

K17

K16

G16

F17

D17

C13

A13

D10

C14

J13

C17

E16

F14

A15

B15

A17

B10

A12

C12

B13

D12

B11

B12

A14

F16

J14

B16

E14

B17

J15

N14

E15

E12

C16

F13

E17

A11

F15

P11

A10

C10

HL_STB

7,37

TP1

0.1UF

C218

0.01UF

C237

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

1.01

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD

OF 36

VCC1_8

CPU

HUB

IRQ

ICH_A

PCI

GND;R2,G3,H8,J8,K8,H9,J9,K9,H10,J10,K10,G14,K15

VCC3_3;E3,A5,E5,G5,N5,E6,P6,T7,C8,U10

VCC3_3;C11,E13,N13,R13,M14,D16,T16

VCC1_8;G13,H14,K14,G15,L15,H16,J16

ICH_096

GPIO1/REQ#B/REQ#5

PIRQD#

PIRQB#

IRQ14

FERR#

AD29

GNT#4

PCIRST#

HL1

A20M#

AD13’

APICCLK

CPUSLP#

INIT#

IRDY#

IRQ15

SERR#

HL4

AD12

AD8

AD9

AD10

AD15

AD14

AD19

AD16

AD26

AD25

AD11

AD20

AD22

AD24

AD23

AD27

AD18

AD17

CBE0#

CBE#1

CBE#2

CBE#3

DEVSEL#

FRAME#

STOP#

TRDY#

PAR

PLOCK#

IGNNE#

INTR

NMI

HL10

HL11

REQ#0

REQ#2

REQ#4

REQ#3

REQ#1

GNT#3

GNT#2

AD31

AD30

AD21

AD28

PIRQC#

STPCLK#

A20GATE

RCIN#

SMI#

APICD0

APICD1

SERIRQ

HUBREF

GPIO16/GNT#A

GPIO17/GNT#B/GNT#5

PCICLK

PIRQA#

GPIO0/REQ#A

GNT#0

GNT#1

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

PERR#/GPIO7

PME#

HL0

HL2

HL3

HL5

HL6

HL7

HL8

HL9

HL_STB

HL_STB#

HLCOMP

VCC1_8

HUBREF voltage = 0.9V +/- 2%

Place HUBREF circuit between MCH and ICH

Place R239 less than 0.5" from the ICH using a 10 mil trace.

Place C237 close to ICH.

ICH