Intel VC820 Design Guide - Page 137
Differential Clock Routing Diagram A', 'C', & 'D
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Clocking For the line section labeled 'D' (DRCG to Last RIMM) the CTM/CTM# must be length matched within ±2 mils (exactly is recommended), and for the section labeled 'C', ±2 mil trace length matching is required for the CFM/CFM# signals. Note: Total trace length matching for the entire CTM/CTM# signal trace (Sections A+B+D) and for the CFM/CFM# signal trace (Sections A+B) is ±2 mils (exact length matching is recommended). Figure 4-6. Differential Clock Routing Diagram (Section 'A', 'C', & 'D') 22 mils Ground 6 mils 14 mils CLOCK 6 mils 14 mils CLOCK# 6 mils 22 mils Ground 2.1 mils 4.5 mils 4.5 mils Ground/Power Plane Figure 4-7. Non-Differential Clock Routing Diagram (Section 'B') 10 mils 18 mils Ground 6 mils CLOCK/CLOCK# 6 mils 10 mils Ground 4.5 mils 4.5 mils 1.4 mils dif lk t d 2.1 mils Ground/Power Plane 1.4 mils The CFM/CFM# differential pair signals require termination using either 27 Ω 1% or 28 Ω 2% resistors and a 0.1 uF capacitor as shown in Figure 4-8. Figure 4-8. Termination for Direct Rambus* Clocking Signals CFM/CFM# CFM R1 28 Ω 2% or 27 Ω 1% CFM# R2 28 Ω 2% or 27 Ω 1% C1 0 .1 uF Intel®820 Chipset Design Guide 4-9