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Intel VC820 Design Guide - Page 175

Super I/O, LPC47B27X

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8 Super I/O 7 VCC3_3 26 VCC5_KBMS_J 9,10,12 9,10,12 RP5 4.7K R315 D 1234 4.7K 9,10,12 9,10,12 9,10,12 9,12 8765 6,8,10,11,12,16,19,20,21,22 KBDAT 26 KBCLK 26 MDAT 26 MCLK 26 9 8,12,21,32 5,12 8,32 8,32 IRRX C 18 IRTX 18 25 C320 C317 25 25 470PF 470PF 25 25 25 25 25 25 25 25 25 25 25 LPC header. For debug only. 25 B J20 25 9,10,12 LAD3/FWH3 1 2 9,10,12 LAD2/FWH2 3 4 26 9,10,12 LAD1/FWH1 5 6 26 9,10,12 LAD0/FWH0 7 8 26 9,10,12 LFRAME#/FWH4 9 10 26 6,8,10,11,12,16,19,20,21,22 PCIRST# 11 12 26 5,12 SIO_PCLK7 13 14 26 9,12 LDRQ#0 15 16 26 17 18 26 5,9 MULT1_GPIO 19 20 26 21 22 26 8,12,21,32 SERIRQ 23 24 26 25 26 26 27 28 26 26 A 5 8 7 6 5 4 3 2 1 VCC5 VCC3_3 VREF 44 VTR 18 VCC1 53 VCC2 65 VCC3 93 C349 + LFRAME#/FWH4 LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 LDRQ#0 PCIRST# LPCPD# LPC_PME# SERIRQ SIO_PCLK7 KBRST# A20GATE RXD0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0 RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 DRVDEN#1 DRVDEN#0 MTR#0 DS#0 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK#0 WRTPRT# RDATA# DSKCHG# SIO_14MHZ 6 U17 24 LFRAME# 23 LAD3 22 LAD2 21 LAD1 20 LAD0 25 LDRQ# 26 LRESET# 27 LPCPD# 17 PME# 30 SERIRQ 29 PCI_CLK 56 KDAT 57 KCLK 58 MDAT 59 MCLK 63 KBDRST 64 A20GATE LPC I/F PARALLEL PORT I/F SIO LPC47B27X KYBD/MSE I/F INIT# 66 PAR_INIT# SLCTIN# 67 SLIN# PD7 75 PDR7 PD6 74 PDR6 PD5 73 PDR5 PD4 72 PDR4 PD3 71 PDR3 PD2 70 PDR2 PD1 69 PDR1 PD0 68 PDR0 SLCT# 77 SLCT PE 78 PE BUSY 79 BUSY ACK# 80 ACK# ERROR# 81 ERR# ALF# 82 AFD# STROBE# 83 STB# 24 PDR[7:0] 24 24 24 24 24 24 24 24 24 VCC5 VCC3_3 D C309 0.1UF C348 C321 C313 C323 0.1UF 0.1UF 0.1UF 0.1UF 1 2 2.2UF Place next to VREF. Place decoupling caps near each power pin. 61 IRRX2/GP34 62 IRTX2/GP35 INFRARED I/F FAN2/GP32 54 FAN1/GP33 55 PWM2 PWM1 18 18 C 84 RXD1 85 TXD1 86 DSR1# 87 RTS1# 88 CTS1# 89 DTR1# 90 RI1# 91 DCD1# FDC_PP/DDRC/GP43 28 SERIAL PORT 1 95 RXD2_IRRX VCC3_3 96 TXD2_IRTX 97 DSR2# 98 RTS2# SERIAL PORT 2 99 CTS2# GP60/LED1 48 R313 4.7K 100 DTR2# GP61/LED2 49 92 RI2# 94 DCD2# GP27/IO_SMI# 50 GP30/FAN_TACH2 51 LPC_SMI# 9 TACH2 18 B GP31/FAN_TACH1 52 CPU_TACH1 2 DRVDEN1 1 DRVDEN0 3 MTR0# GP25/MIDI_IN 46 GP26/MIDI_OUT 47 MIDI_IN 27 MIDI_OUT 27 5 DS0# 8 DIR# 9 STEP# 10 WDATA# 11 WGATE# 12 HDSEL# 13 INDEX# 14 TRK0# 15 WRTPRT# 16 RDATA# FDC I/F GP10/J1B1 32 GP11/J1B2 33 GP12/J2B1 34 GP13/J2B2 35 GP14/J1X 36 GP15/J1Y 37 GP16/J2X 38 GP17/J2Y 39 GP20/P17 41 GP21/P16 42 J1BUTTON1 27 J1BUTTON2 27 J2BUTTON1 27 J2BUTTON2 27 JOY1X 27 JOY1Y 27 JOY2X 27 JOY2Y 27 KEYLOCK# 18 4 DSKCHG# GP22/P12 43 6 CLKI32 CLOCKS GP24/SYSOPT 45 SYSOPT 19 CLOCKI Pulldown on SYSOPT for IO address of 0x02E A 4.7K 7 GND1 31 GND2 60 GND3 76 GND4 40 AVSS R312 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: SUPER I/O 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-18-1999_10:46 12 OF 36 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-18-1999_10:46

SUPER I/O

R313

4.7K

KBCLK

LPC_PME#

U17

100

R312

4.7K

J20

SIO_14MHZ

9,10,12

LAD3/FWH3

9,10,12

LAD1/FWH1

9,10,12

LAD0/FWH0

9,12

LDRQ#0

SIO_PCLK7

5,12

MDAT

MCLK

RXD0

TXD0

DSR#0

RTS#0

CTS#0

DTR#0

RI#0

DCD#0

RXD1

DSR#1

RTS#1

CTS#1

DTR#1

RI#1

DCD#1

MTR#0

DIR#

HDSEL#

INDEX#

TRK#0

SLIN#

RDATA#

PAR_INIT#

DSKCHG#

AFD#

STB#

SLCT

BUSY

ACK#

ERR#

8,32

KBRST#

8,32

A20GATE

SERIRQ

8,12,21,32

PWM1

LPC_SMI#

MIDI_IN

MIDI_OUT

J1BUTTON1

J1BUTTON2

J2BUTTON1

J2BUTTON2

JOY1X

JOY1Y

JOY2X

JOY2Y

9,10,12

LAD2/FWH2

KBDAT

TXD1

TACH2

PWM2

DRVDEN#0

KEYLOCK#

DRVDEN#1

DS#0

STEP#

WDATA#

WGATE#

WRTPRT#

9,10,12

LAD3/FWH3

9,10,12

LAD2/FWH2

9,10,12

LAD1/FWH1

9,10,12

LAD0/FWH0

9,10,12

LFRAME#/FWH4

6,8,10,11,12,16,19,20,21,22 PCIRST#

5,12

SIO_PCLK7

9,12

LDRQ#0

8,12,21,32

SERIRQ

PDR7

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR[7:0]

IRRX

IRTX

6,8,10,11,12,16,19,20,21,22

PCIRST#

5,9

MULT1_GPIO

LPCPD#

SYSOPT

9,10,12

LFRAME#/FWH4

470PF

C320

470PF

C317

0.1UF

C309

0.1UF

C321

C348

0.1UF

C313

0.1UF

C323

2.2UF

C349

VCC5_KBMS_J

4.7K

R315

RP5

4.7K

CPU_TACH1

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

1.01

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD

OF 36

VCC3_3

SIO

LPC47B27X

A20GATE

ACK#

ALF#

AVSS

BUSY

CLKI32

CLOCKI

CTS1#

CTS2#

DCD1#

DCD2#

DIR#

DRVDEN0

DRVDEN1

DS0#

DSKCHG#

DSR1#

DSR2#

DTR1#

DTR2#

ERROR#

FAN1/GP33

FAN2/GP32

FDC_PP/DDRC/GP43

GND1

GND2

GND3

GND4

GP10/J1B1

GP11/J1B2

GP12/J2B1

GP13/J2B2

GP14/J1X

GP15/J1Y

GP16/J2X

GP17/J2Y

GP20/P17

GP21/P16

GP22/P12

GP25/MIDI_IN

GP26/MIDI_OUT

GP27/IO_SMI#

GP30/FAN_TACH2

GP31/FAN_TACH1

GP60/LED1

GP61/LED2

HDSEL#

INDEX#

INIT#

IRRX2/GP34

IRTX2/GP35

KBDRST

KCLK

KDAT

LAD0

LAD1

LAD2

LAD3

LDRQ#

LFRAME#

LRESET#

MCLK

MDAT

MTR0#

PCI_CLK

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PME#

RDATA#

RI1#

RI2#

RTS1#

RTS2#

RXD1

RXD2_IRRX

SERIRQ

SLCT#

SLCTIN#

STEP#

STROBE#

TRK0#

TXD1

TXD2_IRTX

VCC1

VCC2

VCC3

WDATA#

WGATE#

WRTPRT#

VREF

GP24/SYSOPT

VTR

LPCPD#

SERIAL PORT 1

SERIAL PORT 2

FDC I/F

LPC I/F

INFRARED I/F

CLOCKS

KYBD/MSE I/F

PARALLEL PORT I/F

VCC3_3

VCC5

VCC3_3

Pulldown on SYSOPT for IO address of 0x02E

LPC header. For debug only.

Super I/O

Place decoupling caps near each power pin.

Place next to VREF.