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Intel VC820 Design Guide - Page 208

Processor Connector 1, Please see the PentiumR II processor Single Edge

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8 7 Processor Connector 1 3,8 D HD#[63:0] C B A HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 J120 B72 HD#0 A73 HD#1 B71 HD#2 A72 HD#3 B70 HD#4 A71 HD#5 B68 HD#6 B67 HD#7 A69 HD#8 A68 HD#9 A65 HD#10 A64 HD#11 B66 HD#12 A63 HD#13 A67 HD#14 B64 HD#15 A61 HD#16 B63 HD#17 B60 HD#18 B59 HD#19 B62 HD#20 A60 HD#21 B58 HD#22 A59 HD#23 A57 HD#24 B56 HD#25 B55 HD#26 A56 HD#27 B52 HD#28 B54 HD#29 A55 HD#30 A53 HD#31 B51 HD#32 A51 HD#33 B48 HD#34 A52 HD#35 B46 HD#36 A49 HD#37 B50 HD#38 A45 HD#39 B47 HD#40 B42 HD#41 A43 HD#42 A48 HD#43 B44 HD#44 A44 HD#45 A39 HD#46 B43 HD#47 B39 HD#48 A40 HD#49 B35 HD#50 A41 HD#51 B40 HD#52 A36 HD#53 B36 HD#54 A33 HD#55 B34 HD#56 A37 HD#57 B31 HD#58 B38 HD#59 A35 HD#60 A32 HD#61 B30 HD#62 B32 HD#63 8 7 6 SC242 6 5 4 3 2 1 HA#[31:0] 3,8 D HA#3 B98 HA#3 HA#4 A100 HA#4 HA#5 A97 HA#5 HA#6 B99 HA#6 HA#7 B96 HA#7 HA#8 B95 HA#8 HA#9 A99 HA#9 HA#10 A96 HA#10 HA#11 B92 HA#11 HA#12 B94 HA#12 HA#13 A93 HA#13 HA#14 A95 HA#14 HA#15 B90 HA#15 HA#16 A92 HA#16 HA#17 B91 HA#17 HA#18 A91 HA#18 HA#19 A89 HA#19 HA#20 B86 HA#20 HA#21 B87 HA#21 C HA#22 A85 HA#22 HA#23 A87 HA#23 HA#24 B83 HA#24 HA#25 B88 HA#25 HA#26 B82 HA#26 HA#27 A84 HA#27 HA#28 B84 HA#28 HA#29 B80 HA#29 HA#30 A81 HA#30 HA#31 A83 HA#31 HA#32 B79 HA#33 A79 HA#34 A80 HA#35 B78 VID0 VID1 VID2 VID3 VID4 B120 A120 A119 B119 A121 VID1[0] VID1[1] VID1[2] VID1[3] VID1[4] RS#0 RS#1 RS#2 B108 A112 B111 RS#0 RS#1 RS#2 RSP# B115 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 B102 B103 A107 A108 B104 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 RP# B114 THRMDN B15 THRMDN1_R THRMDP B14 THRMDP1_R RESERVED3 RESERVED2 RESERVED1 RESERVED0 B12 A116 A88 A47 5 4 VCC3_3 VCC3_3 VID1[4:0] RS#[2:0] VCC2 2 B U8 30 ADM1021 3 DXP 4 DXN STBY# 15 3,8 ADD0 10 1 NC1 ADD1 6 5 NC5 9 NC9 13 NC13 16 NC16 SMBCLK 14 SMBDATA 12 ALERT# 11 SMBCLK_CORE SMBDATA_CORE THRM# 3,11,13,34 3,11,13,34 3,11 GND8 GND7 HREQ#[4:0] 3,8 7 8 R121 THRMDN1 0K R122 THRMDP1 0K A THRMDP and THRMDN signals must be disconnected from onboard thermal sensor during SECC2 thermal testing of the processor. Please see the "Pentium(R) II processor Single Edge Contact Cartridge 2 Thermal Validation" document for further details. Place R121, R122 very close to processor. TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PROCESSOR CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-30-1999_9:57 5 OF 38 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-30-1999_9:57

PROCESSOR CONNECTOR

ADM1021

R122

R121

3,11,13,34

SMBCLK_CORE

3,11,13,34

SMBDATA_CORE

VID1[4:0]

VID1[0]

VID1[3]

VID1[2]

VID1[1]

VID1[4]

3,8

HA#[31:0]

HA#3

HA#4

HA#5

HA#6

HA#7

HA#8

HA#9

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#30

HA#31

HA#29

HA#10

HREQ#[4:0]

3,8

HREQ#4

HREQ#0

HREQ#1

HREQ#2

HREQ#3

HD#0

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

HD#53

HD#54

HD#55

HD#56

HD#57

HD#58

HD#59

HD#60

HD#61

HD#62

HD#63

HD#26

HD#25

HD#24

HD#23

HD#22

HD#21

HD#20

HD#19

HD#18

HD#17

HD#16

HD#15

HD#14

HD#13

HD#12

HD#11

HD#10

HD#9

HD#8

HD#7

HD#6

HD#5

HD#4

HD#3

HD#2

HD#1

3,8

HD#[63:0]

3,8

RS#[2:0]

RS#2

RS#1

RS#0

3,11

THRM#

THRMDN1_R

THRMDP1_R

THRMDN1

THRMDP1

J120

A47

A88

A116

B119

A121

A119

A120

B120

B98

A100

A97

B78

A80

A79

B79

A83

A81

B80

B84

A84

B82

B88

B83

A87

A85

B87

B86

A89

A91

B91

A92

B90

A95

A93

B94

B92

A96

A99

B95

B96

B99

B114

B102

B103

A107

A108

B104

B115

B108

A112

B111

B32

B30

A32

A35

B38

B31

A37

B34

A33

B36

A36

B40

A41

B35

A40

B43

B39

A39

A44

A48

B44

A43

B42

B47

A45

B50

A49

B46

A52

B48

A51

B51

A53

A55

B54

B52

A56

B55

B56

A57

A59

A60

B58

B59

B62

B60

B63

A61

B64

A63

A67

B66

B72

A73

B71

A72

B70

A71

B68

B67

A69

A68

A65

A64

B12

B15

B14

ADD0

ADD1

SMBCLK

SMBDATA

ALERT#

GND7

GND8

NC16

NC13

NC9

NC5

NC1

DXN

DXP

VCC2

STBY#

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VCC3_3

RESERVED0

RESERVED1

RESERVED2

VID3

VID4

VID2

VID1

VID0