Intel VC820 Design Guide - Page 214

11-29-1999_14:46

11

ICH

GPIO12

GPIO13

R212

8.2K

8.2K

R215

LPC_PME#

14

LPC_SMI#

14

8.2K

R317

8.2K

R254

GPIO21

R98

0K

RTCX1

VBAT_RTC

20

GPIO26_FPLED

AC_SDOUT_STRAP

JP5

1K

R250

8.2K

R232

15,17

AC_BITCLK

9,18,31,33

PWROK

SMBDATA_CORE

3,5,13,34

SMBCLK_CORE

3,5,13,34

17

AC_RST#

15,17

AC_SYNC

15,17

AC_SDATAIN0

17

AC_SDATAIN1

11,20

SPKR

12,14

LAD0/FWH0

LAD1/FWH1

12,14

12,14

LAD2/FWH2

12,14

LAD3/FWH3

LFRAME#/FWH4

12,14

USBP1P

25

USBP1N

25

USBP0P

25

USBP0N

25

24

SIORDY

24

PIORDY

SDIOW#

24

PDIOW#

24

SDIOR#

24

PDIOR#

24

SDDACK#

24

PDDACK#

24

SDREQ

24

PDREQ

24

SDA2

SDA0

24

SDA[2:0]

SDA1

PDA1

PDA0

PDA2

24

PDA[2:0]

24

SDCS#3

24

PDCS#3

SDCS#1

24

PDCS#1

24

OC#1

25

OC#0

25

1K

R230

32.768KHZ

Y4

2

1

31,33

SLP_S3#

PDD14

PDD13

PDD12

PDD11

PDD10

PDD9

PDD8

PDD7

PDD6

PDD5

PDD4

PDD3

PDD2

PDD1

PDD0

PDD[15:0]

24

PDD15

SDD12

SDD13

SDD14

SDD15

SDD11

SDD10

SDD9

SDD8

SDD7

SDD6

SDD5

SDD4

SDD3

SDD2

SDD1

SDD[15:0]

24

SDD0

R233

1K

R245

1K

ICH_CLK66

7

ICH_14MHZ

7

ICH_48MHZ

7

R341

2.7K

MULT0_GPIO

7

34

SMB_ALERT

PWRBTN#

20

27

ICH_RI#

11,20

SPKR

10M

R249

14

LDRQ#0

32

SLP_S5#

INTRUDER#

8.2K

R231

3,5

THRM#

RTC_CLR

GPIO8

SPKR_STRAP

VBAT_CR

VCC5_REF

8.2K

R241

JP26

VBAT_RC

2.7K

R90

RSMRST#

19,33

7,14

MULT1_GPIO

0.047UF

C249

12PF

C251

0.1UF

C233

C250

12PF

1UF

C246

1

2

1UF

C234

2

1

C247

2.2UF

2

1

BAT17

CR5

C

A

BAT17

CR4

A

C

BAT17

CR3

C

A

U13

L5

J3

L1

N1

C15

J4

M1

L4

P16

R17

R15

U17

T15

P14

T14

U14

T13

P13

R14

U15

U16

T17

R16

P15

H1

H3

P10

T10

P9

T9

P8

T8

N7

P7

U8

U7

R7

R8

U9

R9

N9

R10

N17

N11

N15

T11

N16

R11

M13

U12

P17

U11

L13

M15

M16

T12

R12

L16

U13

L14

N12

U4

T4

T5

U5

R6

D15

H4

H2

E11

D11

K4

F1

M2

G1

A16

N4

L2

M5

K2

J1

P3

U6

D13

B14

U1

T2

U2

T3

U3

N3

T6

P1

P2

N2

R1

M3

M4

J2

P12

L3

T1

D14

K3

R3

GPIO23_FPLED

20

ALERTCLK_SBY

18,34

ALERTDATA_SBY

18,34

JP20

3

2

1

RTC_RST_JP

BAT1

1

2

3

VBIAS

RTCX2

R247

10M

11,15,17

AC_SDATAOUT

AC_SDATAOUT

11,15,17

8.2K

R238

7

DRCG_CTRL

23

PCI_TEST

R162

0K

RTCRST#

VCC_RTC_JP

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

8

7

6

5

4

3

2

1

A

B

C

D

1

2

3

4

5

6

7

8

D

C

B

A

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

R

VCC3_3

VCC3_3

VCC5

VCC3_3SBY

XTAL

VCC3_3

VCC3_3SBY

VCC3_3SBY

VCC3_3

+

+

+

-

+

-

+

-

+

SYSTEM

LPC

AC97

USB

GPIO

IDE

ICH_B

ICH_096

AC_BIT_CLK

GPIO24/SLP_S3#

THRM#

AC_RST#

RI#

PDA2

SMBCLK

OC1#

OC0#

USBP1+

USBP0-

USBP1-

USBP0+

LDRQ0#

GPIO8/LDRQ1#

SPKR

AC_SYNC

CLK48

AC_SDOUT

ACSDIN0

GPIO21

GPIO22

CLK14

GPIO9/AC_SDIN1

SMBDATA

SLP_S5#

GPIO27/ALERT_CLK

GPIO13

GPIO12

CLK66

VCCRTC

PWRBTN#

RSMRESET#

SUSCLK/GPIO26

GPIO5

GPIO6

VBIAS

RTCX2

GPIO23

LAD0/FWH0

LAD1/FWH1

LAD2/FWH2

LAD3/FWH3

LFRAME#/FWH4

PDCS1#

SDCS1#

PDCS3#

SDCS3#

PDA0

PDA1

SDA0

SDA1

SDA2

PDDREQ

SDDREQ

PDDACK#

SDDACK#

PDIOR#

SDIOR#

PDIOW#

SDIOW#

PIORDY

SIORDY

PDD0

PDD1

PDD2

PDD3

PDD4

PDD6

PDD7

PDD5

PDD8

PDD9

PDD10

PDD11

PDD12

PDD13

PDD14

PDD15

RTCX1

RTCRST#

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9

SDD10

SDD11

SDD12

SDD13

SDD14

SDD15

GPIO25/SUSSTAT#

GPIO11/SMBALERT#

GPIO10/INTRUDER#

VCC5REF

VCCSUS

VCCSUS1

PWROK

GPIO28/ALERT_DATA

+

ICH

Use CR2032 battery.

Strap

JP26

No WD Reboot

IN

Reboot on WD*

OUT

Strap

JP5

Safe Mode

IN

ICH strap*

OUT

CMOS

JP20

Normal*

1-2

Clear

2-3

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Intel VC820 Design Guide - Page 214

No WD Reboot, Reboot on WD, Safe Mode, ICH strap, Normal, Clear, Strap

Page 214 highlights