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Intel VC820 Design Guide - Page 218

AD1881, PRI_DWN_RST#_R

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8 7 6 5 4 3 2 1 AC'97 Audio VCC3_3 VCC12 VR2 MC78M05CDT D VCC5_AUDIO 15,16 D 0.1UF 0.1UF 0.1UF +5V 3 VCC5_AUDIO 15,16 1 VIN 1 GND 4 1 C77 C49 C21 C62 C48 No stuff C358. 0.1UF 0.1UF C358 2 2 0.1UF C57 + 10UF C83 + 10UF 1 2 L17 AGND AGND VCC3_3 AGND AGND AC97_SPKR R67 20 10K AC97_SPKR_R 0.1UF C76 R66 1K 0.1UF C85 U2 C C 43 NC43 44 NC44 40 NC40 26 AVSS1 25 AVDD1 42 AVSS2 38 AVDD2 9 DVDD2 7 DVSS2 1 DVDD1 4 DVSS1 1UF-TANT C70 2 1 + AC97_SPKR_C 12 PC_BEEP LINE_IN_R 16 24 LINE_IN_R LINE_IN_L 16 23 LINE_IN_L MIC_IN 16 21 MIC1 22 MIC2 CD_R 16 20 CD_R CD_L 16 18 CD_L CD_REF 16 19 CD_REF 17 VIDEO_R AD1881 RESET# 11 SDATA_OUT 5 SDATA_IN 8 SYNC 10 BIT_CLK 6 Series resistors are for test purposes only. PRI_DWN_RST#_R R31 AC_SDATAOUT_R 0K AC_SDATAIN_R R116 0K AC_SYNC_R 0K AC_BITCLK_R R56 0K 0K R77 R106 PRI_DWN_RST# AC_SDATAOUT AC_SDATAIN0 AC_SYNC AC_BITCLK 17 11,17 11,17 11,17 11,17 VCC3_3 C63 MONO_PHONE 2 1 17 + 1UF-TANT C12 MONO_PHONE_C MONO_OUT 2 1 MONO_OUT_C 17 + 1UF-TANT 16 VIDEO_L 14 AUX_L 15 AUX_R 13 PHONE 37 MONO_OUT 36 LINE_OUT_R CS1 46 CS0 45 CHAIN_CLK 48 EAPD 47 C84 10PF No stuff C84 R29 100K No stuff B LNLVL_OUT_R 16 35 LINE_OUT_L 41 LNLVL_OUT_R B LNLVL_OUT_L 16 39 LNLVL_OUT_L EAPD 16 XTL_IN 2 XTL_OUT 3 VREFOUT 28 VREF 27 AC_VREF_C CX3D RX3D FILT_R FILT_L AFLIT2 AFILT1 34 CX3D_C 33 RX3D_C 31 FILT_R_C 32 30 29 AFILT1_C AFILT2_C FILT_L_C AUD_VREFOUT 16 AC_XTAL_IN AC_XTAL_OUT Y1 XTAL 1 2 24.576MHZ R28 100K No stuff C16 0.1UF 22PF C94 22PF C95 10UF-TANT +C9 1 0.1UF C20 0.047UF C17 1UF-TANT +C1 1 C18 1 +C7 2 270PF-NPO 2 1UF-TANT 270PF-NPO C19 A A 2 AGND AGND TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 15 OF 38 8 7 6 5 4 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:46

AUDIO

AC_BITCLK

11,17

0.1UF

C358

PRI_DWN_RST#

11,17

AC_SDATAOUT

AC_SDATAIN0

11,17

AC_SYNC

11,17

R56

R106

R77

RX3D_C

CD_REF

LINE_IN_L

CD_L

CD_R

AC97_SPKR

AUD_VREFOUT

10K

R67

R66

LINE_IN_R

24.576MHZ

MIC_IN

MONO_PHONE

15,16

VCC5_AUDIO

100K

R28

LNLVL_OUT_L

15,16

VCC5_AUDIO

LNLVL_OUT_R

L17

AC97_SPKR_R

AC97_SPKR_C

MONO_PHONE_C

AFILT1_C

AFILT2_C

FILT_L_C

AC_XTAL_IN

AC_XTAL_OUT

AC_VREF_C

FILT_R_C

CX3D_C

R29

100K

R31

PRI_DWN_RST#_R

AC_SDATAOUT_R

AC_SDATAIN_R

AC_SYNC_R

AC_BITCLK_R

R116

MONO_OUT_C

MONO_OUT

0.1UF

C62

C83

10UF

C57

10UF

0.1UF

C85

1UF-TANT

C70

0.1UF

C77

0.1UF

C49

C21

0.1UF

C76

1UF-TANT

C63

1UF-TANT

C12

C19

270PF-NPO

C18

270PF-NPO

22PF

C95

22PF

C94

1UF-TANT

C20

0.1UF

0.047UF

C17

C16

0.1UF

10UF-TANT

VR2

0.1UF

C48

EAPD

10PF

C84

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

AGND

AFILT1

AFLIT2

AUX_L

AUX_R

AVDD1

AVDD2

AVSS1

AVSS2

BIT_CLK

CD_REF

CD_L

CD_R

CHAIN_CLK

EAPD

CS0

CS1

CX3D

DVDD1

DVDD2

DVSS1

DVSS2

FILT_L

FILT_R

LINE_IN_L

LINE_IN_R

LINE_OUT_L

LINE_OUT_R

LNLVL_OUT_L

LNLVL_OUT_R

MIC1

MIC2

MONO_OUT

NC40

NC43

NC44

PC_BEEP

PHONE

RESET#

RX3D

SDATA_IN

SDATA_OUT

SYNC

VIDEO_L

VIDEO_R

VREF

VREFOUT

XTL_IN

XTL_OUT

AD1881

AGND

VCC3_3

XTAL

AGND

VCC12

AGND

MC78M05CDT

VIN

+5V

GND

AGND

No stuff

Series resistors are for test purposes only.

No stuff C358.

AC’97 Audio

No stuff C84