Intel VC820 Design Guide - Page 122
High Frequency Decoupling, Layer Switch with Multiple Reference Planes
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Advanced System Bus Design When routing and stackup constraints require that an AGTL+ signal reference VCC or multiple planes, special care must be given to minimize the SSO impact to timing and noise margin. The best method of reducing adverse effects is to add high-frequency decoupling wherever the transitions occur, as shown in Figure 3-9 and Figure 3-10. Such decoupling should, again, be in the vicinity of the signal transition via and use capacitors with minimal effective series resistance (ESR) and effective series inductance (ESL). When placing the caps it is recommended to space the VSS and VCC vias as close as possible and/or use dual vias since the via inductance may sometimes be higher than the actual capacitor inductance. Figure 3-9. Layer Switch with Multiple Reference Planes Signal Layer A Power Plane Layer Layer Ground Plane Signal Layer B Figure 3-10. One Layer with Multiple Reference Planes Signal Layer A Ground Power 3.4.3.3 High Frequency Decoupling 1l M lt f l d This section contains several high frequency decoupling recommendations that will improve the return path for an AGTL+ signal. These design recommendations will very likely reduce the amount of SSO effects. Just as layer switching and multiple reference planes can create discontinuities in an AGTL+ signal return path, discontinuities may also occur when a signal transitions between the baseboard and cartridge. Therefore, providing adequate high-frequency decoupling across VCCCORE and ground at the SC242 connector interface on the baseboard will minimize the discontinuity in the signal's reference plane at this junction. Note that these additional high-frequency decoupling capacitors are in addition to the high-frequency decoupling already on the processor. Transmission line geometry also influences the return path of the reference plane. The following are decoupling recommendations that take this into consideration: • A signal that transitions from a stripline to another stripline should have close proximity decoupling between all four reference planes. • A signal that transitions from a stripline to a microstrip (or vice versa) should have close proximity decoupling between the three reference planes. • A signal that transitions from a stripline or microstrip through vias or pins to a component (Intel 82820 MCH, etc.) should have close proximity decoupling across all involved reference planes to ground for the device. 3-22 Intel®820 Chipset Design Guide