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Pci Connectors 1 And 2

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8 7 PCI Connectors 0 and 1 VCC3_3 VCC12- VCC5 PCI Slot 0 J12 PCI3_CON B1 A1 PTCK B2 A2 D 22,23 B3 A3 B4 A4 B5 A5 B6 A6 10,21,22,23,34 PIRQ#B B7 A7 10,22,23,34 PIRQ#D B8 A8 PRSNT#11 22 B9 A9 B10 A10 PRSNT#12 22 B11 A11 B12 A12 B13 A13 B14 A14 B15 A15 PCLK1 7 B16 A16 B17 A17 10,34 PREQ#0 B18 A18 B19 A19 AD31 B20 A20 C AD29 B21 A21 B22 A22 AD27 B23 A23 AD25 B24 A24 B25 A25 C_BE#3 B26 A26 AD23 B27 A27 B28 A28 AD21 B29 A29 AD19 B30 A30 B31 A31 AD17 B32 A32 C_BE#2 B33 A33 10,18,22,23,34 IRDY# B34 A34 B35 A35 10,18,22,23,34 DEVSEL# B36 A36 B37 A37 10,22,23,34 PLOCK# B38 A38 B39 A39 10,18,22,23,34 PERR# B40 A40 B B41 A41 10,18,22,23,34 SERR# B42 A42 B43 A43 C_BE#1 B44 A44 AD14 B45 A45 B46 A46 AD12 B47 A47 AD10 B48 A48 B49 A49 AD8 B52 A52 AD7 B53 A53 B54 A54 AD5 B55 A55 AD3 B56 A56 B57 A57 A AD1 B58 A58 B59 A59 PU1_ACK64# B60 A60 22 B61 A61 B62 A62 10,18,23 C_BE#[3:0] 10,18,23 AD[31:0] 8 7 R74 5.6K 5.6K R367 R79 5.6K R72 5.6K key key 6 5 4 VCC3_3 VCC5 VCC12 VCC3_3 VCC12- VCC5 PTRST# 22,23 PTMS 22,23 PTDI 22,23 22,23 PIRQ#A PIRQ#C 10,18,21,22,23,34 10,22,23,34 VCC3_3SBY PTCK 10,22,23,34 10,18,21,22,23,34 22 22 PIRQ#C PIRQ#A PRSNT#21 PRSNT#22 PCIRST# 8,10,12,13,14,18,21,22,23,24 PGNT#0 10,34 PCI_PME# 10,18,21,22,23 AD30 AD28 AD26 AD24 R_AD16 22 AD22 AD20 AD18 AD16 10,18,22,23,34 FRAME# 10,18,22,23,34 TRDY# 10,18,22,23,34 STOP# SDONEP1 22 SBOP1 22 PAR 10,18,22,23 AD15 AD13 AD11 AD9 PCLK2 7 PREQ#1 10,34 AD31 AD29 AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 IRDY# DEVSEL# PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10 PCI Slot 1 J11 PCI3_CON B1 A1 B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 B8 A8 B9 A9 B10 A10 B11 A11 B12 A12 B13 A13 B14 A14 B15 A15 B16 A16 B17 A17 B18 A18 B19 A19 B20 A20 B21 A21 B22 A22 B23 A23 B24 A24 B25 A25 B26 A26 B27 A27 B28 A28 B29 A29 B30 A30 B31 A31 B32 A32 B33 A33 B34 A34 B35 A35 B36 A36 B37 A37 B38 A38 B39 A39 B40 A40 B41 A41 B42 A42 B43 A43 B44 A44 B45 A45 B46 A46 B47 A47 B48 A48 B49 A49 C_BE#0 AD6 AD4 AD2 AD0 PU1_REQ64# 22 AD8 AD7 AD5 AD3 AD1 PU2_ACK64# 22 B52 A52 B53 A53 B54 A54 B55 A55 B56 A56 B57 A57 B58 A58 B59 A59 B60 A60 B61 A61 B62 A62 6 5 4 3 VCC5 VCC5 VCC3_3 VCC12 VCC5 2 1 For pullups, see 4.3.3 of PCI 2.1 Specification PTRST# PTMS 22,23 PTDI 22,23 22,23 VCC5 D PIRQ#B PIRQ#D 10,21,22,23,34 10,22,23,34 VCC3_3SBY 22 SDONEP1 SDONEP2 22 SBOP1 22 SBOP2 22 RP12 1 8 2 7 3 6 4 5 5.6K PCIRST# 8,10,12,13,14,18,21,22,23,24 C117 0.1UF PRSNT#11 22 PGNT#1 PCI_PME# AD30 10,34 10,18,21,22,23 C123 0.1UF PRSNT#12 22 C113 0.1UF PRSNT#21 22 AD28 AD26 C122 0.1UF C PRSNT#22 22 AD24 R_AD17 22 AD22 AD20 AD18 AD16 FRAME# TRDY# STOP# SDONEP2 SBOP2 PAR AD15 VCC5 22 PU1_ACK64# R178 22 PU1_REQ64# 2.7K R179 2.7K 22 PU2_ACK64# R176 B 2.7K 22 PU2_REQ64# R177 2.7K AD13 AD11 AD9 C_BE#0 AD6 AD4 AD16 R120 R_AD16 10,18,22,23 22 100 AD17 R119 R_AD17 10,18,22,23 22 100 AD2 AD0 A PU2_REQ64# 22 TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: PCI CONNECTORS 1 AND 2 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 22 OF 38 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

PCI CONNECTORS 1 AND 2

11-29-1999_14:46

22,23

PTCK

10,21,22,23,34

PIRQ#B

10,22,23,34

PIRQ#D

PCLK1

10,34

PREQ#0

C_BE#1

C_BE#0

C_BE#2

C_BE#3

C_BE#0

C_BE#3

C_BE#2

C_BE#1

10,18,23

C_BE#[3:0]

10,18,22,23,34

IRDY#

10,18,22,23,34

DEVSEL#

10,22,23,34

PLOCK#

10,18,22,23,34

SERR#

10,18,22,23

PAR

10,18,22,23,34

TRDY#

10,18,22,23,34

FRAME#

10,22,23,34

PIRQ#C

10,18,21,22,23,34

PIRQ#A

22,23

PTDI

22,23

PTMS

22,23

PTCK

10,34

PGNT#1

10,34

PREQ#1

PCLK2

SDONEP1

SDONEP2

SBOP1

SBOP2

PRSNT#11

PRSNT#12

PRSNT#21

PRSNT#22

PU1_ACK64#

PU1_REQ64#

PU2_ACK64#

PU2_REQ64#

R_AD16

R_AD17

22,23

PTRST#

5.6K

R74

5.6K

R367

5.6K

R79

5.6K

R72

100

R120

100

R119

5.6K

RP12

2.7K

R178

2.7K

R179

2.7K

R176

2.7K

R177

22,23

PTDI

22,23

PTMS

10,18,22,23,34

STOP#

10,18,21,22,23

PCI_PME#

8,10,12,13,14,18,21,22,23,24

PCIRST#

10,34

PGNT#0

R_AD17

PRSNT#11

PRSNT#12

10,18,22,23,34

PERR#

SBOP1

SDONEP1

IRDY#

DEVSEL#

PLOCK#

SERR#

R_AD16

22,23

PTRST#

PRSNT#21

PRSNT#22

8,10,12,13,14,18,21,22,23,24

PCIRST#

10,18,21,22,23

PCI_PME#

FRAME#

TRDY#

STOP#

SDONEP2

SBOP2

PAR

10,18,22,23

AD16

10,18,22,23

AD17

PERR#

10,21,22,23,34

PIRQ#B

10,22,23,34

PIRQ#D

10,22,23,34

PIRQ#C

10,18,21,22,23,34

PIRQ#A

AD25

10,18,23

AD[31:0]

AD30

AD3

AD5

AD7

AD17

AD31

AD29

AD27

AD25

AD23

AD19

AD14

AD12

AD10

AD8

AD1

AD2

AD4

AD6

AD9

AD11

AD13

AD15

AD16

AD18

AD20

AD22

AD24

AD26

AD30

AD28

AD0

AD28

AD26

AD24

AD22

AD20

AD18

AD13

AD11

AD9

AD6

AD4

AD2

AD1

AD10

AD12

AD14

AD19

AD21

AD23

AD27

AD29

AD31

AD17

AD7

AD5

AD3

AD8

AD16

AD15

AD21

PU2_REQ64#

PU2_ACK64#

PU1_REQ64#

PU1_ACK64#

0.1UF

C117

0.1UF

C123

0.1UF

C113

0.1UF

C122

J11

A21

A27

A33

A39

A45

B25

B31

B36

B43

A53

B54

A10

A16

A59

A61

A62

B59

B61

B62

B19

B60

A58

B58

B48

A47

B47

A46

B45

A44

A32

B32

A31

B30

A57

A29

B29

A28

B27

A25

B24

A23

B23

A22

B21

B56

A20

B20

A55

B55

A54

B53

B52

A49

A52

B44

B33

B26

B16

B37

A34

A12

A13

A18

A24

A30

A35

A37

A42

A48

B12

B13

B15

B17

B22

B34

B38

B46

B49

A56

B57

B28

A17

A26

B35

B39

A43

B40

A19

B11

B18

A60

A11

A14

B10

B14

A15

A41

A40

B42

A38

A36

B41

J12

B41

A36

A38

B42

A40

A41

A15

B14

B10

A14

A11

A60

B18

B11

A19

B40

A43

B39

B35

A26

A17

B28

B57

A56

B49

B46

B38

B34

B22

B17

B15

B13

B12

A48

A42

A37

A35

A30

A24

A18

A13

A12

A34

B37

B16

B26

B33

B44

A52

A49

B52

B53

A54

B55

A55

B20

A20

B56

B21

A22

B23

A23

B24

A25

B27

A28

B29

A29

A57

B30

A31

B32

A32

A44

B45

A46

B47

A47

B48

B58

A58

B60

B19

B62

B61

B59

A62

A61

A59

A16

A10

B54

A53

B43

B36

B31

B25

A45

A39

A33

A27

A21

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VCC3_3SBY

VCC5

VCC12-

VCC3_3

VCC12

VCC3_3

VCC12-

VCC12

VCC3_3

VCC5

VCC3_3SBY

PCI3_CON

key

PCI3_CON

key

PCI Slot 0

For pullups, see 4.3.3 of PCI 2.1 Specification

PCI Slot 1

0 and 1

PCI Connectors