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Voltage Regulators, VCC 5V DUAL VOLTAGE SWITCHER

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8 7 6 5 4 3 2 1 Voltage Regulators AGP VDDQ VOLTAGE REGULATOR VCC 5V DUAL VOLTAGE SWITCHER The VCC5DUAL plane should not drive any logic components requiring 5V. It should be used only for further regulation of lower voltage power planes because the true voltage of VCC5DUAL will not remain constant D Rdson of the FET is not negligible for large currents VCC5SBY VCC12 C347 47UF VCC5 C324 47UF VCC5DUAL R330 1K VCC12 1 2 VCC3_3 1 2 C173 + 47UF D VDDQ C193 + 10UF SN74LVC07A has 5V input and output tolerance. VCC5SBY VCC3_3SBY VCC5SBY 14 R331 1K C U18 9,31 SLP_S3# 74LS1432 14VCC 6 PWROK 5 U14 VCC 1 2 7,9,16,31 VD_G1 7 VD_G2 7 GND GND SN74LVC07A VCC5DUAL_R Q12 SI4562DY 1 S1 2 G1 3 S2 4 G2 D1 8 D1A 7 D2 6 D2A 5 Q13 C R340 3 B1 1K VD_G3 2 E MMBT3904LT1 VCC1_8 C352 + 1500UF C336 + 1500UF 1 1 2 2 VCC3_3 R218 1K R363 0K C174 + 1UF No stuff R363 1 2 220UF 1+ 2 C160 VR6 LT1575 1 SHDN 2 VIN 3 GND 4 FB IPOS 8 Q6 3 INEG GATE 7 6 VDDQ_G R135 VDDQ_G2 1 1 3 COMP 5 5.1-5% 2 2 VDDQ_COMP C164 10PF 2 + 1VDDQ_COMP_R R137 C168 0.001UF 7.5K-1% R141 IRL2203NS C 11111 22222 301 1% C200 + 1UF-X7R C225 + 1UF-X7R C211 + 1UF-X7R C179 + 1UF-X7R C242 + 22UF R158 2.2K VCC3_3 VTT1_5 VTT 1.5 VOLTAGE REGULATOR VR4 LT1587-1_5 VOUT 2 3 VIN 1 1 1 GND 1 C142 + 100UF C124 + 100UF C104 + 1UF-X7R 2 2 2 B R361 1K VR_SHUTDOWN Q16 C 3 VR_SDB B 1 2 E MMBT3904LT1 TYPEDET# 19 R360 10K Q7 C 3 B1 2 E MMBT3904LT1 VDDQ_FB R146 1.21K-1% Route VR6 GND to VDDQ output caps and then via to ground. B R362 1K VCC3_3 1 VCC 1.8 VOLTAGE REGULATOR VR8 LT1587ADJ VOUT 2 3 VIN 1 ADJ 1 VCC1_8_ADJ R311 301-1% C333 + 100UF C108 + 100UF C311 + 100UF VCC1_8 VCC2_5SBY 1 1 1 + BAT17 AC CR11 VCC5 VCC2_5 VOLTAGE REGULATOR VR5 LT1587ADJ 2 2 2 VOUT 2 3 VIN 1 1 ADJ 1 VCC2_5_ADJ R134 100-1% VCC2_5 1 2 VCC5DUAL VCC3_3SBY VCC3_3SBY VOLTAGE REGULATOR VR1 LT1529-3_3 5 VIN VOUT 1 1 1 4 SHDN# SENSE 2 1 2 2 2 C91 + 100UF TAB 6 GND3 3 C35 + 1UF-X7R C15 + 330UF-T510 C167 + 100UF A 2 2 2 2 A C161 + 1UF-X7R C159 + 100UF R133 100-1% C268 + 1UF-X7R C319 + 100UF R309 131-1% Place C311 at regulator. Place C108 and C333 at RIMM termination 8 7 6 5 4 TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: VOLTAGE REGULATORS 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-18-1999_11:24 29 OF 36 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-18-1999_11:24

VOLTAGE REGULATORS

100UF

C333

100UF

C108

100-1%

R133

100-1%

R134

301-1%

R311

131-1%

R309

5.1-5%

R135

R146

1.21K-1%

R141

301

7,9,16,31

PWROK

R331

9,31

SLP_S3#

VR8

U18

VR4

LT1587-1_5

VD_G2

VD_G1

VD_G3

VCC1_8_ADJ

VCC2_5_ADJ

VDDQ_FB

VDDQ_COMP_R

7.5K-1%

R137

VDDQ_G

VDDQ_G2

U14

C324

47UF

1UF-X7R

C104

1UF-X7R

C268

100UF

C124

100UF

C142

100UF

C319

C159

100UF

C167

1UF-X7R

C35

C161

1UF-X7R

C91

100UF

C193

10UF

C174

1UF

47UF

C173

1UF-X7R

C200

C225

1UF-X7R

C211

C179

1UF-X7R

VR5

C160

220UF

VDDQ_COMP

330UF-T510

C15

LT1575

VR6

10PF

C164

C168

0.001UF

22UF

C242

LT1529-3_3

VR1

1500UF

C352

1500UF

C336

R340

C311

100UF

R330

C347

47UF

VCC5DUAL_R

R158

2.2K

R360

10K

TYPEDET#

R361

R362

VR_SDB

R218

VR_SHUTDOWN

R363

CR11

BAT17

MMBT3904LT1

Q16

MMBT3904LT1

Q13

SI4562DY

Q12

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

1.01

TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD

OF 36

VCC3_3

VCC2_5SBY

VCC3_3SBY

VCC5

VCC2_5

VCC5DUAL

VCC5

VTT1_5

VCC3_3

VCC3_3SBY

VCC3_3

VCC5DUAL

VCC12

VCC5SBY

VIN

VOUT

ADJ

LT1587ADJ

74LS132

VCC

GND

VCC5SBY

VIN

VOUT

GND

SN74LVC07A

GND

VCC

VDDQ

VIN

VOUT

ADJ

LT1587ADJ

IPOS

INEG

GATE

COMP

SHDN

VIN

GND

VIN

VOUT

SHDN#

GND3

TAB

SENSE

VCC5SBY

VCC3_3

VCC1_8

IRL2203NS

D2A

D1A

It should be used only for further regulation of lower voltage power planes

The VCC5DUAL plane should not drive any logic components requiring 5V.

because the true voltage of VCC5DUAL will not remain constant

Rdson of the FET is not negligible for large currents

VTT 1.5 VOLTAGE REGULATOR

VCC3_3SBY VOLTAGE REGULATOR

AGP VDDQ VOLTAGE REGULATOR

VCC 5V DUAL VOLTAGE SWITCHER

VCC2_5 VOLTAGE REGULATOR

VCC 1.8 VOLTAGE REGULATOR

Route VR6 GND to VDDQ output caps and then via to ground.

Voltage Regulators

Place C311 at regulator.

Place C108 and C333 at RIMM termination

SN74LVC07A has 5V input and output tolerance.

No stuff R363