Intel VC820 Design Guide - Page 80
In-Target Probe ITP, Logic Analyzer Interface LAI
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Layout/Routing Guidelines The recommendation for the layout and the schematic example are shown below. Layout guidelines are: • Place the transistor and stub as close as possible to MCH (or place the transistor pad on top of trace) • The max stub for transistor is less than 0.25" • The recommended loading of transistor is less than 5 pf. • For dual processor design, the stub is recommended to place on the stub of the MCH and as close as possible to the MCH, and is less than 0.25" Note: This circuit is only recommended for the debug situation that requires to set the IOQ depth equal to 1. For the production, do not add this circuit, since the overall system performance will be degraded. Also, Intel does not guarantee the above layout recommendation will work under the worst case condition. Figure 2-45. HA7# Strapping Option Example Circuit (For Debug Purposes Only) 5V 5V 5V R2 CPURST# 4.7 KΩ R2 2.7 KΩ 2N3904 4 2 D /PRE Q 5 3 CLK /Q 6 /CLR 1 74F74 4 2 D /PRE Q 5 3 CLK /Q 6 /CLR 1 74F74 4.7 KΩ jumper R2 4.7 KΩ HA7 2N3904 CPUCLK In-Target Probe (ITP) It is important that all of the processor electrical characteristic requirements are met. It is recommended that prototype boards implement the ITP connector. Logic Analyzer Interface (LAI) Note that 1 KΩ resistors that are used to pull-up several processor signals in the schematics in Appendix A, "Reference Design Schematics: Uni-Processor" and Appendix B, "Reference Design Schematics: Dual-Processor" (e.g., HINIT#, IGNNE#, SMI#, etc.) preclude use of the Intel Pentium III processor LAI. The Intel Pentium III processor LAI will function correctly with these 1 KΩ pull-up resistors. 2-54 Intel®820 Chipset Design Guide