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AC'97_RISER, Audio Down

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R68 R108 10K R125 10K 8 7 6 5 4 3 2 AC'97 Audio/Modem Riser D VCC3_3SBY VCC3_3 VCC5 VCC12 VCC12- VCC3_3SBY 4.7K U3 14 PRI_DWN_RST# 6 4 PRI_DWN_U 5 C 15 SN774LVC08A 3 MONO_OUT 15 PRI_DWN# 1 JP2 2 11,15 11 AC_SDATAOUT AC_RST# Audio Down JP2 Enable* 1-2 B Disable 2-3 J8 B1 AUDIO_MUTE# B2 GND[0] (ISOLATED) AUDIO_PWRDWN A1 MONO_PHONE A2 B3 MONO_OUT/PC_BEEP B4 RESV[1] B5 RESV[2] B6 PRIMARY_DN# B7 -12V RESV[5] A3 RESV[6] A4 RESV[7] A5 GND[7] A6 +5VDUAL/5VSBY A7 B8 GND[1] USB_OC A8 B9 +12V B10 GND[2] GND[8] A9 USB+ A10 B11 +5VD AC'97_RISER USB- A11 KEY KEY B12 GND[3] B13 RESV[3] B14 RESV[4] AMR_CONNECTOR KEY KEY GND[9] A12 S/P_DIF_IN A13 GND[10] A14 B15 +3.3VD B16 GND[4] B17 AC97_SDATA_OUT B18 AC97_RESET# B19 AC97_SDATA_IN3 +3VDUAL/3VSBY A15 GND[11] A16 AC97_SYNC A17 GND[12] A18 AC97_SDATA_IN1 A19 B20 GND[5] GND[13] A20 B21 AC97_SDATA_IN2 B22 GND[6] AC97_SDATA_IN0 A21 GND[14] A22 B23 AC97_MSTRCLK AC97_BITCLK A23 VCC5 VCC3_3SBY AC_SDATAIN1_R R113 0K MONO_PHONE 15 AC97_OC# 25 AC97_USB+ 25 AC97_USB25 AC_SYNC 11,15 AC_SDATAIN1 11 AC_SDATAIN0 11,15 AC_BITCLK 11,15 1 D C B A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AUDIO/MODEM RISER 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 17 OF 38 8 7 6 5 4 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

AUDIO/MODEM RISER

R125

10K

11,15

AC_BITCLK

11,15

AC_SYNC

MONO_OUT

11,15

AC_SDATAOUT

MONO_PHONE

JP2

PRI_DWN#

PRI_DWN_U

R68

4.7K

AC97_USB+

AC97_USB-

AC_RST#

PRI_DWN_RST#

AC97_OC#

A11

A10

A13

B14

B13

A12

B22

B20

B16

B12

B10

A22

A20

A18

A16

A14

A17

B17

B19

B21

A19

A21

B18

B23

A23

B11

A15

B15

AC_SDATAIN1_R

R113

AC_SDATAIN0

11,15

AC_SDATAIN1

R108

10K

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VCC12-

VCC12

VCC3_3SBY

VCC5

VCC3_3

SN74LVC08A

AC’97_RISER

AMR_CONNECTOR

KEY

+12V

+3.3VD

+3VDUAL/3VSBY

+5VD

+5VDUAL/5VSBY

-12V

AC97_BITCLK

AC97_MSTRCLK

AC97_RESET#

AC97_SDATA_IN0

AC97_SDATA_IN1

AC97_SDATA_IN2

AC97_SDATA_IN3

AC97_SDATA_OUT

AC97_SYNC

AUDIO_MUTE#

AUDIO_PWRDWN

(ISOLATED)

GND[0]

GND[10]

GND[11]

GND[12]

GND[13]

GND[14]

GND[1]

GND[2]

GND[3]

GND[4]

GND[5]

GND[6]

GND[7]

GND[8]

GND[9]

MONO_OUT/PC_BEEP

MONO_PHONE

RESV[1]

RESV[2]

RESV[3]

RESV[4]

RESV[5]

RESV[6]

RESV[7]

S/P_DIF_IN

PRIMARY_DN#

USB+

USB-

USB_OC

AC’97 Audio/Modem Riser

Audio Down

JP2

Enable*

1-2

Disable

2-3