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Intel VC820 Design Guide - Page 239

RIMM Decoupling, Decoupling., ICH Decoupling, MCH Decoupling

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8 7 6 5 4 3 2 1 Decoupling MCH Decoupling ICH Decoupling 82559 Decoupling. RIMM Decoupling C290 C88 C105 C60 C29 C30 C252 C230 C224 C254 C248 C232 C231 C253 C162 C202 C213 C156 C166 C201 C212 C157 D VCC1_8 VCC2_5SBY VCC2_5SBY VCMOS1_8SBY D VCC3_3 VCC3_3SBY C219 C285 C210 C303 C302 C289 C284 C288 C235 C264 C226 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF C258 C229 C227 C222 VCC1_8 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 4.7UF Place a VCMOS1_8SBY 0.1uF cap at each RIMM. 0.01UF Place these caps on solder side 0.01UF C VDDQ 0.01UF 0.01UF 0.1UF Place 100uF caps, 0.1 ohm ESR, among RIMM connectors. C C255 C165 For chipset decoupling, use 0.1UF and 0.01UF decoupling capacitor at each corner of the device. If there is room, add 0.01UF capacitors in the middle of each quad. 0.1UF Place these caps on solder side VCC3_3SBY Un-used Gates VCC3_3SBY C143 C144 C197 C272 C270 C221 VDDQ 0.01UF 0.01UF B 0.01UF 0.01UF 0.01UF 0.01UF Place VDDQ capacitors within 70 mils of outer balls of MCH. A 8 7 VCC3_3SBY U14 VCC 14 9 8 7 GND SN74LVC07A U14 VCC 14 11 10 7 GND SN74LVC07A 6 9 14 U3 8 10 SN74LVC087A 12 14 U3 11 13 SN74LVC087A VCC5SBY U18 74LS1132 14VCC 3 2 7 GND U18 74LS11232 14VCC 11 13 7 GND 5 4 U15 14 11 10 74LVC14A7 U15 14 13 12 74LVC14A7 VCC3_3SBY U20 14VCC 9 8 SN74LVC06A7 GND U20 14VCC 11 10 SN74LVC06A7 GND U20 14VCC 13 12 SN74LVC06A7 GND 3 VCC3_3 U19 VCC 14 3 4 B 7 GND SN74LVC07A U19 VCC 14 11 10 7 GND SN74LVC07A U19 VCC 14 13 12 7 GND SN74LVC07A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: DECOUPLING 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:44 36 OF 38 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:44

DECOUPLING

0.1UF

C60

C29

0.1UF

C30

C157

0.1UF

C212

C201

0.1UF

C166

0.1UF

C156

0.01UF

C213

C202

0.01UF

C162

0.01UF

0.1UF

C253

0.1UF

C231

C232

0.1UF

C248

0.1UF

C254

0.01UF

C224

C230

0.01UF

C252

0.01UF

C222

0.1UF

C227

0.1UF

C229

C258

0.1UF

C165

C210

100UF

C285

C219

100UF

C288

100UF

C284

C289

100UF

C303

100UF

C302

C226

0.1UF

C264

C235

0.1UF

C255

0.1UF

C105

0.1UF

4.7UF

C88

C290

4.7UF

U15

U20

U14

U18

U14

U19

U18

C221

0.01UF

C270

C272

0.01UF

C197

C144

0.01UF

C143

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VDDQ

VCC1_8

VCC5SBY

VCC3_3

VCMOS1_8SBY

VCC2_5SBY

SN74LVC08A

74LVC14A

VCC3_3SBY

SN74LVC06A

GND

VCC

SN74LVC06A

GND

VCC

SN74LVC06A

GND

VCC

SN74LVC07A

GND

VCC

74LS132

VCC

GND

VCC3_3SBY

SN74LVC07A

GND

VCC

VCC3_3SBY

SN74LVC07A

GND

VCC

SN74LVC07A

GND

VCC

SN74LVC07A

GND

VCC

74LS132

VCC

GND

VCC3_3SBY

VCC3_3

VCC1_8

VDDQ

Place these caps on solder side

70 mils of outer balls of MCH.

Place VDDQ capacitors within

For chipset decoupling, use 0.1UF and

0.01UF decoupling capacitor at each

corner of the device.

If there is room,

add 0.01UF capacitors in the middle

of each quad.

Place 100uF caps, 0.1 ohm ESR, among RIMM connectors.

Place a VCMOS1_8SBY 0.1uF cap at each RIMM.

Un-used Gates

RIMM Decoupling

82559 Decoupling.

ICH Decoupling

MCH Decoupling

Decoupling