Intel VC820 Design Guide - Page 222
No stuff JP1, JP3, JP4, R60, R73, R78., C79.
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8 7 LAN D 6 5 4 VCC3_3 3 2 VCC3_3 1 D R73 330 R78 330 R60 330 SPEED_J JP4 ACT_J LI_J R61 LI_CR 330 R366 ACT_CR 330 TD_C TDP 18 Place termination resistors close to 82559. R26 49.9-1% J2 JP3 JP1 No stuff JP1,JP3,JP4,R60,R73,R78. TDN 18 R20 49.9-1% 10 TD+ RJMAG 14 12 TD- LILED C 18 RD_C RDP R62 49.9-1% RJ-45 9 RD+ 13 7 RD- 16 LILED 18,19 18,19 18,19 ACTLED SPEEDLED R364 3 RJ-4 18 C No stuff C61, C79. C61 C79 49.9-1% 4 RJ-5 15 ACTLED 18,19 0.1UF 18 0.1UF RDN 5 RJ-7 6 RJ-8 TDC_J 11 TDC 8 RDC 2 TXC 1 RXC 17 SHLD1 18 SHLD2 RJ_7_J RJ4_J TXC_J RDC_J 11,33 18 For debug only. Hold LAN in reset. J18 RSMRST# 1 LAN_RSMRST# 2 3 R10 75 RXC_J R365 75 R8 75 C31 C78 R6 75 0.1UF 0.1UF XC_R 82559 LAN J17 B C5 No stuff C5. Enable* 1-2 B 470PF C5 must be rated at 1500V. No stuff C31. Disable 2-3 A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: LAN 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: 11-29-1999_14:46 SHEET: 19 OF 38 8 7 6 5 4 3 2 1