Intel VC820 Design Guide - Page 197
Un-used Gates, Decoupling
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8 7 6 5 4 3 2 1 Decoupling MCH Decoupling D VCC1_8 VCC1_8 ICH Decoupling VCC3_3 82559 Decoupling. VCC3_3SBY 0.1UF 0.1UF 0.1UF 0.1UF C290 C88 C105 C60 C29 C30 C252 C230 C224 C254 C248 C232 C231 C253 C260 C184 C265 C257 C197 C221 C202 C213 C156 C201 C212 C157 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF 0.1UF 0.1UF 0.01UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF Place these caps on solder side 0.01UF 0.01UF 4.7UF 4.7UF 0.1UF VDDQ C 0.01UF 0.1UF 0.01UF 0.01UF 0.01UF C258 C219 C285 C210 C303 C366 C365 C302 C289 C284 C288 C235 C264 C226 RIMM Decoupling D VCC2_5SBY VCC2_5SBY VCMOS1_8SBY 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Place 100uF caps, 0.1 ohm ESR, among RIMM connectors. Place a VCMOS1_8SBY 0.1uF cap at each RIMM. C C262 C261 For chipset decoupling, use 0.1UF and 0.01UF decoupling capacitor at each corner of the device. If there is room, add 0.01UF capacitors in the middle of each quad. Place these caps on solder side VDDQ Un-used Gates VCC3_3SBY VCC3_3SBY 9 14 U3 8 10 SN74LVC087A U15 14 11 10 74LVC14A7 VCC3_3 C343 C344 0.01UF 0.01UF B U15 14 12 14 U3 13 12 U19 VCC 14 11 13 74LVC14A7 3 4 B 7 SN74LVC087A GND SN74LVC07A C166 0.01UF VCC3_3SBY VCC3_3SBY VCC5SBY U19 VCC 14 11 10 C367 C162 0.01UF 7 U20 14VCC GND 9 8 SN74LVC07A 0.01UF U14 VCC 14 9 8 U18 74LS1132 14VCC 3 SN74LVC06A7 GND 2 U19 VCC 7 14 GND SN74LVC07A 7 GND U20 14VCC 13 12 C368 0.01UF 11 10 7 GND U14 VCC U18 SN74LVC06A7 GND SN74LVC07A 14 11 10 74LS11232 14VCC 11 A GND SN74LVC07A 7 13 7 GND U20 14VCC 13 12 A Place VDDQ capacitors within SN74LVC06A7 GND 70 mils of outer balls of MCH. TITLE: INTEL(R) 820 CHIPSET CUSTOMER REFERENCE BOARD REV: DECOUPLING 1.01 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-30-1999_10:26 34 OF 36 8 7 6 5 4 3 2 1