Intel VC820 Design Guide - Page 138
DRCG Impedance Matching Circuit, DRCG Impedance Matching Network
View all Intel VC820 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 138 highlights
Clocking 4.3 DRCG Impedance Matching Circuit The external DRCG impedance matching circuit is shown in Figure 4-9. The values for the elements are listed in Table 4-5. Figure 4-9. DRCG Impedance Matching Network To 3.3V DRCG Supply Connection 3.3v FBead CD V DD IR CD V DDO V DD P CD DRCG CD V DD C V DD IPD CD VDDO R S CF R S CD CD2 CD2 ZCH R P C MID R P ZCH CBulk RT CMID2 RT Table 4-5. External DRCG Component Values1,2 Component CD RS RP CMID, CMID2 RT CF FBead CD2 CBulk Nominal Value 0.1 uF 39 Ohms 51 Ohms 0.1 uF 27 Ohms 4 pF 50 Ohms at 100 MHz 0.1 uF 10 uF Notes Decoupling caps to ground Series termination resistor Parallel termination resistor Virtual ground caps End of channel termination Do not stuff Ferrite bead Additional 3.3V decoupling caps Bulk cap on device side of ferrite bead NOTES: 1. The ferrite bead and 10 uF bulk cap combination improves jitter and helps to keep the clock noise away from the rest of the system. 2. 0.1 uF capacitors are better than 0.01 uF or 0.001 uF caps for DRCG decoupling. The circuit shown in Figure 4-9 is required to match the impedance of the DRCG to the 28 Ω channel impedance. More detailed information can be found in the Direct Rambus Clock Generator Specification. 4-10 Intel®820 Chipset Design Guide