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Intel VC820 Design Guide - Page 224

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8 7 6 5 4 VCC3_3 AGP Connector D 10,22,23,34 C B A SBA[7:0] 9 9 ST[2:0] PIRQ#B 7 VCC3_3SBY 9 GAD[31:0] 9 GC/BE#[3:0] VCC5 J13 25 AGP_OC# B1 OVRCNT# B2 5V_A B3 5V_B USBAGP+ B4 25 USB+ B5 GND_K B6 INTB# AGPCLK_CONN B7 CLK 9,34 GREQ# B8 REQ# B9 VCC3_3_F ST0 B10 ST0 ST2 B11 ST2 9,34 RBF# B12 RBF# B13 GND_L B14 RESV_H SBA0 B15 SBA0 B16 VCC3_3_G SBA2 B17 SBA2 9,34 SBSTB B18 SB_STB B19 GND_M SBA4 B20 SBA4 SBA6 B21 SBA6 B22 RESV B23 GND_N B24 3_3VAUX1 B25 VCC3_3_H GAD31 B26 AD31 GAD29 B27 AD29 B28 VCC3_3_I GAD27 B29 AD27 GAD25 B30 AD25 B31 GND_O 9,34 GAD23 ADSTB1 B32 AD_STB1 B33 AD23 B34 VDDQ_F GAD21 B35 AD21 GAD19 B36 AD19 B37 GND_P GAD17 B38 AD17 GC/BE#2 B39 C/BE2# B40 VDDQ_G 9,34 GIRDY# B41 IRDY# B42 3_3VAUX2 B43 GND_Q B44 RESV_K B45 VCC3_3_J GDEVSEL# 9,34 B46 DEVSEL# B47 VDDQ_H GPERR# 34 B48 PERR# B49 GND_R 34 GC/BE#1 GSERR# B50 SERR# B51 C/BE1# B52 VDDQ_I GAD14 B53 AD14 GAD12 B54 AD12 B55 GND_S GAD10 B56 AD10 GAD8 B57 AD8 B58 VDDQ_J 9,34 GAD7 ADSTB0 B59 AD_STB0 B60 AD7 B61 GND_T GAD5 B62 AD5 GAD3 B63 AD3 B64 VDDQ_K GAD1 B65 AD1 8 MCH_AGPREF B66 VREF_CG AGP4XU_20 12V A1 A2 TYPEDET# RESV_A A3 USB- A4 A5 GND_A INTA# A6 RST# A7 GNT# A8 VCC3_3_A A9 ST1 A10 RESV_B A11 PIPE# A12 A13 GND_B WBF# A14 SBA1 A15 VCC3_3_B A16 SBA3 A17 A18 SB_STB# GND_C A19 SBA5 A20 SBA7 A21 RESV_C A22 GND_D A23 RESV_D A24 VCC3_3_C A25 AD30 A26 A27 AD28 A28 VCC3_3_D AD26 A29 AD24 A30 GND_E A31 AD_STB1# A32 C/BE3# A33 VDDQ_A A34 AD22 A35 AD20 A36 GND_F A37 A38 AD18 AD16 A39 VDDQ_B A40 FRAME# A41 RESV_E A42 GND_G A43 RESV_F A44 VCC3_3_E A45 TRDY# A46 STOP# A47 PME# A48 A49 GND_H A50 PAR AD15 A51 VDDQ_C A52 AD13 A53 AD11 A54 GND_I A55 AD9 A56 C/BE0# A57 VDDQ_D A58 AD_STB0# A59 AD6 A60 GND_J A61 AD4 A62 A63 AD2 VDDQ_E A64 AD0 A65 VREF_GC A66 8 7 6 5 4 3 2 1 VDDQ VCC12 TYPEDET# USBAGP- 25 PCIRST# GGNT# 9,34 ST1 PIPE# WBF# 9,34 9,34 SBA1 SBSTB# SBA3 9,34 SBA5 SBA7 GAD30 GAD28 GAD26 GAD24 ADSTB#1 GC/BE#3 GAD22 GAD20 GAD18 GAD16 GFRAME# 9,34 21,31 D PIRQ#A 8,10,12,13,14,18,22,23,24 10,18,22,23,34 VDDQ C R193 AGPREF circuitry should be placed close to MCH. 301-1% CON_AGPREF_Q Q8 3 3 9,34 TYPEDET# 21,31 11 2 2 2N7002LT1 R208 200-1% B GTRDY# GSTOP# PCI_PME# 9,34 9,34 10,18,22,23 GPAR 9,34 GAD15 GAD13 GAD11 GAD9 GC/BE#0 ADSTB#0 9,34 GAD6 GAD4 GAD2 GAD0 3 CONN_AGPREF 8 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: AGP CONNECTOR 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-30-1999_10:10 21 OF 38 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-30-1999_10:10

AGP CONNECTOR

21,31

TYPEDET#

R208

200-1%

GAD[31:0]

GAD0

GAD2

GAD4

GAD6

GAD9

GAD11

GAD13

GAD15

GAD16

GAD18

GAD20

GAD22

GAD24

GAD26

GAD28

GAD30

GAD1

GAD3

GAD5

GAD7

GAD8

GAD10

GAD12

GAD14

GAD17

GAD19

GAD21

GAD23

GAD25

GAD27

GAD29

GAD31

AGP_OC#

AGPCLK_CONN

9,34

GREQ#

ST0

ST1

ST2

ST[2:0]

9,34

RBF#

SBA0

SBA2

SBA4

SBA6

SBA5

SBA7

SBA3

SBA1

SBA[7:0]

9,34

SBSTB

9,34

ADSTB1

GC/BE#2

GC/BE#0

GC/BE#3

GC/BE#1

GC/BE#[3:0]

9,34

GIRDY#

9,34

GDEVSEL#

GPERR#

GSERR#

9,34

ADSTB0

9,34

ADSTB#0

9,34

GPAR

10,18,22,23

PCI_PME#

9,34

GSTOP#

9,34

GTRDY#

9,34

GFRAME#

9,34

ADSTB#1

9,34

SBSTB#

9,34

WBF#

9,34

PIPE#

9,34

GGNT#

8,10,12,13,14,18,22,23,24

PCIRST#

USBAGP-

21,31

TYPEDET#

10,18,22,23,34

PIRQ#A

10,22,23,34

PIRQ#B

R193

301-1%

USBAGP+

MCH_AGPREF

CONN_AGPREF

CON_AGPREF_Q

J13

B42

B24

A66

B66

B65

B64

B63

B62

B61

B60

B59

B58

B57

B56

B55

B54

B53

B52

B51

B50

A65

A64

A63

A62

A61

A60

A59

A58

A57

A56

A55

A54

A53

A52

A51

A50

B49

B48

A49

A48

A47

A46

A45

A44

A43

A42

A41

B47

B46

B45

B44

B43

B41

A35

A36

A37

A38

A39

A40

B40

B39

B38

B37

B36

B35

B34

A34

A33

A32

A31

A30

A29

A28

A27

A26

B33

B32

B31

B30

B29

B28

B27

B26

B16

B25

A25

A24

B23

B22

A23

A22

B21

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

B14

A11

A10

B20

B19

B18

B17

B15

B13

B12

B11

B10

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VDDQ

VCC3_3

VCC12

VCC3_3SBY

VCC5

2N7002LT1

AGP4XU_20

OVRCNT#

5V_A

5V_B

USB+

GND_K

INTB#

CLK

REQ#

VCC3_3_F

ST0

ST2

RBF#

GND_L

SBA0

SBA2

SB_STB

GND_M

SBA4

12V

TYPEDET#

RESV_A

USB-

GND_A

INTA#

RST#

GNT#

VCC3_3_A

ST1

RESV_B

RESV_H

PIPE#

GND_B

WBF#

SBA1

VCC3_3_B

SBA3

SB_STB#

GND_C

SBA5

SBA7

SBA6

RESV_C

GND_D

RESV

GND_N

RESV_D

VCC3_3_C

VCC3_3_H

VCC3_3_G

AD31

AD29

VCC3_3_I

AD27

AD25

GND_O

AD_STB1

AD23

AD30

AD28

VCC3_3_D

AD26

AD24

GND_E

AD_STB1#

C/BE3#

VDDQ_A

VDDQ_F

AD21

AD19

GND_P

AD17

C/BE2#

VDDQ_G

VDDQ_B

AD16

AD18

GND_F

AD20

AD22

IRDY#

GND_Q

RESV_K

VCC3_3_J

DEVSEL#

VDDQ_H

FRAME#

RESV_E

GND_G

RESV_F

VCC3_3_E

TRDY#

STOP#

PME#

GND_H

PERR#

GND_R

PAR

AD15

VDDQ_C

AD13

AD11

GND_I

AD9

C/BE0#

VDDQ_D

AD_STB0#

AD6

GND_J

AD4

AD2

VDDQ_E

AD0

SERR#

C/BE1#

VDDQ_I

AD14

AD12

GND_S

AD10

AD8

VDDQ_J

AD_STB0

AD7

GND_T

AD5

AD3

VDDQ_K

AD1

VREF_CG

VREF_GC

3_3VAUX1

3_3VAUX2

AGPREF circuitry should be placed close to MCH.

AGP Connector