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Good DRCG Output Network Layout, CTM/CTM# Routed Properly

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Layout/Routing Guidelines - Vterm island should be 50 - 75 mils wide - Vterm island should not be broken - If any RSL signals are routed out of the last RIMM (towards termination) on the bottom side (even for a short distance), ensure Ground Reference Plane (on the third layer) is continuous under the termination resistors/capacitors - Ensure current path for power delivery to the MCH does not go through the Vterm island • CTM/CTM# Routed Properly - CTM/CTM# are routed differentially from DRCG to last RIMM - CTM/CTM# are ground isolated from DRCG to last RIMM - CTM/CTM# are ground referenced from DRCG to last RIMM - Vias are placed in ground isolation and ground reference every ½" - When CTM/CTM# serpentine together, they MUST maintain EXACTLY 6 mils spacing • Clean DRCG Power Supply - 3.3V DRCG power flood on the top layer. This should connect to each - High frequency (0.1 uF) capacitors are near the DRCG power pins. One capacitor next to each power pin. - 10uF bulk tantalum capacitor near DRCG connected directly to the 3.3V DRCG power flood on the top layer - Ferrite bead isolating DRCG power flood from 3.3V main power also connecting directly to the 3.3VDRCG power flood on the top layer - Use 2 vias on the ground side of each • Good DRCG Output Network Layout - Series resistors (39 Ω) should be VERY near CTM/CTM# pins - Parallel resistors (51 Ω) should be very near series resistors - CTM/CTM# should be 18mils wide from the CTM/CTM# pins to the resistors - CTM/CTM# should be 14 on 6 routed differential as soon as possible after the resistor network - When not 14 on 6, the clocks should be 18 mils wide - Ensure CTM/CTM# are ground referenced and the ground reference is connected to the ground plane every ½" to 1" - Ensure CTM/CTM# are ground isolated and the ground isolation is connected to the ground plane every ½" to 1" - Ensure 15 pf EMI capacitors to ground are removed (the pads are not necessary and removing the pads provides more space for better placement of other components) - Ensure the 4 pf EMI capacitor is implemented (but do not assemble the capacitor) • Good RSL Transmission Lines - RSL traces are 18 mils wide - When RSL traces neck down to exit MCH BGA, the minimum width is 15 mils and the neckdown is no longer than 25 mils in length - RSL traces do NOT neckdown when routing into the RIMM connector - If tight serpentining is necessary, 10 mil ground isolation MUST be between serpentine segments (i.e., an RSL signal CAN NOT serpentine so tightly that the signal is adjacent to itself with no ground isolation between the serpentines). - RSL traces do not cross power plane splits. RSL signals must also not be routed on next to a power plane splits (e.g., the RSL signals on the 4th layer can not be routed directly below the ground isolation split on the 3rd layer) - Uniform ground isolation flood is exactly 6 mils from the RSL signals at all times Intel®820 Chipset Design Guide 2-29

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

Intel

820 Chipset

Design Guide

2-29

Layout/Routing Guidelines

—

Vterm island should be 50 – 75 mils wide

—

Vterm island should not be broken

—

If any RSL signals are routed out of the last RIMM (towards termination) on the bottom

side (even for a short distance), ensure Ground Reference Plane (on the third layer) is

continuous under the termination resistors/capacitors

—

Ensure current path for power delivery to the MCH does not go through the Vterm island

•

CTM/CTM# Routed Properly

—

CTM/CTM# are routed differentially from DRCG to last RIMM

—

CTM/CTM# are ground isolated from DRCG to last RIMM

—

CTM/CTM# are ground referenced from DRCG to last RIMM

—

Vias are placed in ground isolation and ground reference every ½”

—

When CTM/CTM# serpentine together, they MUST maintain EXACTLY 6 mils spacing

•

Clean DRCG Power Supply

—

3.3V DRCG power flood on the top layer. This should connect to each

—

High frequency (0.1 uF) capacitors are near the DRCG power pins. One capacitor next to

each power pin.

—

10uF bulk

tantalum

capacitor near DRCG connected directly to the 3.3V DRCG power

flood on the top layer

—

Ferrite bead isolating DRCG power flood from 3.3V main power also connecting directly

to the 3.3VDRCG power flood on the top layer

—

Use 2 vias on the ground side of each

•

Good DRCG Output Network Layout

—

Series resistors (39

Ω

) should be VERY near CTM/CTM# pins

—

Parallel resistors (51

Ω

) should be very near series resistors

—

CTM/CTM# should be 18mils wide from the CTM/CTM# pins to the resistors

—

CTM/CTM# should be 14 on 6 routed differential as soon as possible after the resistor

network

—

When not 14 on 6, the clocks should be 18 mils wide

—

Ensure CTM/CTM# are ground referenced and the ground reference is connected to the

ground plane every ½” to 1”

—

Ensure CTM/CTM# are ground isolated and the ground isolation is connected to the

ground plane every ½” to 1”

—

Ensure 15 pf EMI capacitors to ground are removed (the pads are not necessary and

removing the pads provides more space for better placement of other components)

—

Ensure the 4 pf EMI capacitor is implemented (but do not assemble the capacitor)

•

Good RSL Transmission Lines

—

RSL traces are 18 mils wide

—

When RSL traces neck down to exit MCH BGA, the minimum width is 15 mils and the

neckdown is no longer than 25 mils in length

—

RSL traces do NOT neckdown when routing into the RIMM connector

—

If tight serpentining is necessary, 10 mil ground isolation MUST be between serpentine

segments (i.e., an RSL signal CAN NOT serpentine so tightly that the signal is adjacent to

itself with no ground isolation between the serpentines).

—

RSL traces do not cross power plane splits. RSL signals must also not be routed

on next to

a power plane splits (e.g., the RSL signals on the 4

layer can not be routed directly below

the ground isolation split on the 3

layer)

—

Uniform ground isolation flood is exactly 6 mils from the RSL signals at all times