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Intel VC820 Design Guide - Page 223

Onboard Spkr, TACH2, Speaker Circuit

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8 7 System D VCC5 VCC5 VCC3_3 R345 10K R344 10K 14 14 7 7 IDEACTP# 24 U19 VCC 1 2 GND SN74LVC07A VCC3_3 C U19 VCC IDEACTS# 24 9 8 GND SN74LVC07A JP25 1 SPKR 2 11 3 Onboard Spkr E nable* Disable JP25 2-3 1-2 B A 6 5 4 3 2 1 VCC3_3SBY VCC3_3 No stuff. For test only 1 1 C350 + 0.1UF 50V C356 + 10UF 16V 0.1UF R316 4.7K R252 1M R359 100K SW1 IDE_ACTIVE AC97_SPKR 15 PC_BEEP ICH has internal pullup and debounce on PWRBTN# 0K R257 PWRBTN# 11 C267 14 No stuff. 1UF For test only 14 IRRX IRTX PWRBTN_FP# HDLED_R R356 470 C354 470PF C355 470PF VCC3_3 VCC5 R354 10K KEYLOCK# 14 R350 2.2K Speaker Circuit SPKR_Q Q15 C 3 P_BEEP B 1 2 E R352 68 R353 68 C353 5%R358 4.7K VCC5 2 2 SPKR_FP J25 1 82 2 IRTX_R 3 R357 5% 4 5 KEY 6 7 8 9 10 11 12 13 KEY 14 15 16 KEY 17 R355 220 18 PLED_R 19 20 KEY KEY 21 22 23 24 KEY 25 26 FNT_PNL_CONN VCC5 SP1 1 + POS 2 NEG SPKR_ONBOARD INFRARED POWER SW. H.D. LED POWER LED KEYLOCK SPEAKER D VCC12 TACH2 C316 VCC3_3 JP22 1 2 3 TACH2 VCC12 PWM1 C 0.1UF R329 4.7K C327 VCC3_3 JP24 1 2 3 PWM1 14 VCC12 PWM2 MMBT3904LT1 14 0.1UF VCC3_3SBY B VCC3_3 CR7 7 R246 330 R253 330 7 R234 4.7K R289 330 SBY_LED_CR 2 1 Onboard LED indicates the standby well is on to prevent hot swapping memory. For debug only. C322 14 0.1UF R326 4.7K VCC3_3SBY VCC3_3SBY VCC3_3SBY VCC3_3SBY JP23 1 2 3 U14 VCC 11 GPIO23_FPLED 3 4 GND SN74LVC07A LED_PU0 1 2 LED_PU1 CR6 DUAL_COLOR VCC U14 65 PWM2 14 PWM outputs from SIO need power buffers for driving fan inputs. GPIO26_FPLED11 GND SN74LVC07A A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: SYSTEM 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 20 OF 38 8 7 6 5 4 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:46

SYSTEM

GPIO23_FPLED

U14

R253

330

IRRX

R252

SP1

IDEACTS#

IDEACTP#

R345

10K

R344

10K

R352

R353

JP24

JP23

R326

4.7K

JP22

4.7K

R316

PWM1

R329

4.7K

R350

2.2K

SPKR

P_BEEP

JP25

AC97_SPKR

IDE_ACTIVE

PWRBTN#

TACH2

R257

R357

IRTX

J25

470

R356

R358

4.7K

KEYLOCK#

R355

220

R289

330

CR7

IRTX_R

HDLED_R

PLED_R

PWRBTN_FP#

SPKR_FP

SPKR_Q

SPKR_ONBOARD

SBY_LED_CR

PC_BEEP

U19

DUAL_COLOR

CR6

LED_PU0

LED_PU1

GPIO26_FPLED

330

R246

4.7K

R234

C267

1UF

470PF

C354

470PF

C355

R359

100K

0.1UF

C327

C316

0.1UF

10K

R354

C322

0.1UF

C350

0.1UF

50V

C356

10UF

16V

0.1UF

C353

MMBT3904LT1

Q15

PWM2

SW1

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

SN74LVC07A

GND

VCC

VCC3_3SBY

SN74LVC07A

GND

VCC

VCC3_3

VCC3_3SBY

VCC5

VCC3_3SBY

VCC3_3

VCC5

NEG

POS

VCC5

VCC12

VCC3_3

FNT_PNL_CONN

VCC3_3

VCC5

VCC3_3

SN74LVC07A

GND

VCC

VCC3_3SBY

SN74LVC07A

GND

VCC

VCC3_3SBY

KEY

No stuff.

For test only

No stuff.

KEY

INFRARED

H.D. LED

PWM1

TACH2

PWM2

SPEAKER

POWER SW.

For test only

ICH has internal pullup and debounce on PWRBTN#

KEY

Speaker Circuit

KEY

KEYLOCK

POWER LED

Onboard LED indicates the standby well is on

PWM outputs from SIO need power buffers for driving fan inputs.

to prevent hot swapping memory.

For debug only.

System

Onboard Spkr

JP25

Enable*

2-3

Disable

1-2