Home » Intel Manuals » Motherboards » Intel VC820 » Manual Viewer

Intel VC820 Design Guide - Page 233

VID Override Jumpers, VRM

Add to My Manuals
Save this manual to your list of manuals

Page 233 highlights

8 7 6 VRM VRM requirements are based on VRM8.4 spec . 5 4 VCC12 L19 1UH R71 5.1-5% C97 + 1UF-X7R VCC5 D PVCC_R 1 2 DO3316P-102 Place caps next to output FETs. C82,C87,C107,C111 must support >6A of RMS current. VRM_VCC5 1 1 1 1 1 R80 10K C140 + 10UF C90 0.1UF C87 + 1200UF C111 + 1200UF C107 + 1200UF C82 + 1200UF 2 2 2 2 2 1 2 C72 + 0.01UF R54 2.7K VCC 5 PVCC 2 VR3 VRM_IMAX C VID[4:0] 3 VID0 RP21 1 8 VID1 2 7 VID2 3 6 VID3 4 5 VID4 0K 0K R398 OUTEN VID0_R VID1_R VID2_R VID3_R VID4_R 19 OUTEN 18 VID0 17 VID1 16 VID2 15 VID3 14 VID4 IMAX 7 PWRGD 13 FAULT# 12 G1 20 IFB 8 G2 1 VFB 11 VRM_FAULT VRM_G1 VRM_IFB VRM_G2 10 COMP 9 SS 4 SGND 3 GND 6 SENSE VID Override Jumpers Default JP6-JP10 OUT. Remove RP21, R398 for VID override. JP6 JP8 JP10 JP7 JP9 LTC1753 VRM_COMP VRM_VFB VRM_SS 3 2 1 VCC3_3 VCC5 R332 220 R53 5.6K D VRM_PWRGD 33 C118, C119 must be next to FETs. C118 + 1UF-X7R 5678 5678 1 D1 D2 D3 D4 D1 D2 D3 D4 Q2 SI4410DY Q3 SI4410DY 2 VCCVID S1 S2 S3 G1 S1 S2 S3 G1 C 4321 4321 L18 R65 IFB_Q 20 1.0UH-20A ETQP6F0R8L 5678 5678 D1 D2 D3 D4 D1 D2 D3 D4 1 C119 + 1UF-X7R Q5 SI4410DY Q4 SI4410DY G1 S3 4321 S2 S1 G1 S3 S2 S1 2 4321 C71 1000PF C86 0.1UF No Stuff C106 C75 0.1UF R55 8.2K 150PF C73 C74 VRM_COMP_R 0.01UF VCCVID1 VCC12 VCC5 B J14 VRM8_4 A1 V5_IN0 V5_IN3 B1 A2 V5_IN1 V5_IN4 B2 A3 V5_IN2 V5_IN5 B3 A4 V12_IN0 V12_IN1 B4 A5 V12_IN2 RSV B5 30 VID1_0R 30 VID1_2R 30 VID1_4R A6 ISHARE OUT_EN B6 A7 VID0 VID1 B7 A8 VID2 VID3 B8 A9 VID4 PWR_GOOD B9 A10 V_OUT0 GND5 B10 A11 GND0 V_OUT6 B11 A12 V_OUT1 GND6 B12 A13 GND1 V_OUT7 B13 A14 V_OUT2 GND7 B14 A15 GND2 V_OUT8 B15 A A16 V_OUT3 GND8 B16 A17 GND3 V_OUT9 B17 A18 V_OUT4 GND9 B18 A19 GND4 V_OUT10 B19 A20 V_OUT5 GND10 B20 VCC5 VCC12 VCCVID1 VCC3_3 VCC3_3 R371 10K R370 220 VID1_1R 30 VID1_3R 30 VRM1_PWRGD 33 8 7 6 C100 + 2200UF C93 + 2200UF C103 + 2200UF C366 + 2200UF 1 1 1 1 B 2 2 2 2 Sanyo 4SP2200M 5 VID1[4:0] VID1[0] VID1[1] VID1[2] VID1[3] VID1[4] RP24 1 8 2 7 3 6 4 5 0K 0K R104 VID Override Jumpers Default JP16, JP27-JP30 OUT. Remove RP24, R104 for VID override. 5 4 VID1_0R 30 VID1_1R 30 VID1_2R 30 VID1_3R 30 VID1_4R 30 JP16 JP27 JP29 JP28 JP30 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: VRM 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET: 11-29-1999_14:46 30 OF 38 3 2 1

Section	Page
Introduction 1	13
1.1 About This Design Guide	13
1.2 References	14
1.3 System Overview	14
1.3.1 Chipset Components	15
1.3.2 Bandwidth Summary	16
1.3.3 System Configuration	17
1.4 Platform Initiatives	20
1.4.1 Direct Rambus*	20
1.4.2 Streaming SIMD Extensions	20
1.4.3 AGP 2.0	20
1.4.4 Hub Interface	20
1.4.5 Manageability	21
1.4.6 AC’97	22
1.4.7 Low Pin Count (LPC) Interface	23
Layout/Routing Guidelines 2	27
2.1 General Recommendations	27
2.2 Component Quadrant Layout	27
2.3 Intel® 820 Chipset Component Placement	29
2.4 Core Chipset Routing Recommendations	30
2.5 Source Synchronous Strobing	31
2.6 Direct Rambus* Interface	33
2.6.1 Stackup	34
2.6.2 Direct Rambus* Layout Guidelines	34
2.6.2.1 RSL Routing	34
2.6.2.2 RSL Termination	37
2.6.2.3 Direct Rambus* Ground Plane Reference	39
2.6.2.4 Direct Rambus* Connector Compensation	40
2.6.2.5 RSL Signal Layer Alternation	46
2.6.2.6 Length Matching Methods	47
2.6.2.7 VIA Compensation	49
2.6.2.8 Length Matching & Via Compensation Example	49
2.6.3 Direct Rambus* Reference Voltage	51
2.6.4 High-speed CMOS Routing	51
2.6.4.1 SIO Routing	52
2.6.4.2 Suspend-to-RAM Shunt Transistor	52
2.6.5 Direct Rambus* Clock Routing	54
2.6.6 Direct Rambus* Design Checklist	54
2.7 AGP 2.0	57
2.7.1 AGP Interface Signal Groups	58
2.7.2 1X Timing Domain Routing Guidelines	59
2.7.3 2X/4X Timing Domain Routing Guidelines	59
2.7.4 AGP 2.0 Routing Summary	61
2.7.5 AGP Clock Routing	62
2.7.6 General AGP Routing Guidelines	62
2.7.7 VDDQ Generation and TYPEDET#	63
2.7.8 VREF Generation for AGP 2.0 (2X and 4X)	65
2.7.9 Compensation	67
2.7.10 AGP Pull-ups	67
2.7.10.1 AGP Signal Voltage Tolerance List	68
2.7.11 Motherboard / Add-in Card Interoperability	68
2.8 Hub Interface	69
2.8.1 Data Signals	70
2.8.2 Strobe Signals	70
2.8.3 HREF Generation/Distribution	70
2.8.4 Compensation	71
2.9 System Bus Design	72
2.9.1 100/133 MHz System Bus	72
2.9.2 System Bus Ground Plane Reference	73
2.10 S.E.C.C. 2 Grounding Retention Mechanism (GRM)	73
2.11 Processor CMOS Pullup Values	75
2.12 Additional Host Bus Guidelines	78
2.13 Ultra ATA/66	82
2.13.1 Ultra ATA/66 Detection	82
2.13.2 Ultra ATA/66 Cable Detection	83
2.13.3 Ultra ATA/66 Pullup/Pulldown Requirements	86
2.14 AC’97	87
2.14.1 AC’97 Signal Quality Requirements	89
2.14.2 AC’97 Motherboard Implementation	89
2.15 USB	91
2.16 ISA (82380AB)	92
2.16.1 ICH GPIO connected to 82380AB	92
2.16.2 Sub Class Code	92
2.17 IOAPIC Design Recommendation	92
2.18 SMBus/Alert Bus	93
2.19 PCI	93
2.20 RTC	93
2.20.1 RTC Crystal	94
2.20.2 External Capacitors	94
2.20.3 RTC Layout Considerations	95
2.20.4 RTC External Battery Connection	95
2.20.5 RTC External RTCRST Circuit	96
2.20.6 RTC Routing Guidelines	96
2.20.7 VBIAS DC Voltage and Noise Measurements	97
Advanced System Bus Design 3	101
3.1 Terminology and Definitions	101
3.2 AGTL+ Design Guidelines	104
3.2.1 Initial Timing Analysis	105
3.2.2 Determine General Topology, Layout, and Routing Desired	108
3.2.3 Pre-Layout Simulation	108
3.2.3.1 Methodology	108
3.2.3.2 Sensitivity Analysis	108
3.2.3.3 Monte Carlo Analysis	109
3.2.3.4 Simulation Criteria	109
3.2.4 Place and Route Board	110
3.2.4.1 Estimate Component To Component Spacing for AGTL+ Signals	110
3.2.4.2 Layout and Route Board	110
3.2.4.3 Host Clock Routing	112
3.2.4.4 APIC Data Bus Routing	112
3.2.5 Post-Layout Simulation	113
3.2.5.1 Intersymbol Interference	113
3.2.5.2 Cross-Talk Analysis	113
3.2.5.3 Monte Carlo Analysis	113
3.2.6 Validation	114
3.2.6.1 Measurements	114
3.2.6.2 Flight Time Simulation	114
3.2.6.3 Flight Time Hardware Validation	115
3.3 Theory	115
3.3.1 AGTL+	115
3.3.2 Timing Requirements	116
3.3.3 Cross-talk Theory	116
3.3.3.1 Potential Termination Cross-Talk Problems	118
3.4 More Details and Insight	119
3.4.1 Textbook Timing Equations	119
3.4.2 Effective Impedance and Tolerance/Variation	120
3.4.3 Power/Reference Planes, PCB Stackup, and High Frequency Decoupling	120
3.4.3.1 Power Distribution	120
3.4.3.2 Reference Planes and PCB Stackup	121
3.4.3.3 High Frequency Decoupling	122
3.4.3.4 SC242 Connector	123
3.4.4 Clock Routing	123
3.5 Definitions of Flight Time Measurements/ Corrections and Signal Quality	124
3.5.1 VREF Guardband	124
3.5.2 Ringback Levels	124
3.5.3 Overdrive Region	124
3.5.4 Flight Time Definition and Measurement	125
3.6 Conclusion	126
Clocking 4	129
4.1 Clock Generation	129
4.2 Component Placement and Interconnection Layout Requirements	134
4.2.1 14.318MHz Crystal to CK133	134
4.2.2 CK133 to DRCG	134
4.2.3 MCH to DRCG	135
4.2.4 DRCG to RDRAM Channel	136
4.2.5 Trace Length	136
4.3 DRCG Impedance Matching Circuit	138
4.3.1 DRCG Layout Example	139
4.4 AGP Clock Routing Guidelines	139
4.5 Series Termination Resistors for CK133 Clock Outputs	139
4.6 Unused Outputs	140
4.7 Decoupling Recommendation for CK133 and DRCG	140
4.8 DRCG Frequency Selection and the DRCG+	140
4.8.1 DRCG Frequency Selection Table and Jitter Specification	140
4.8.2 DRCG+ Frequency Selection Schematic	141
System Manufacturing 5	145
5.1 In Circuit FWH Flash BIOS Programming	145
5.2 FWH Flash BIOS Vpp Design Guidelines	145
5.3 Stackup Requirement	145
5.3.1 Overview	145
5.3.2 PCB Materials	146
5.3.3 Design Process	146
5.3.4 Test Coupon Design Guidelines	147
5.3.5 Recommended Stackup	147
5.3.6 Inner Layer Routing	147
5.3.7 Impedance Calculation Tools	148
5.3.8 Testing Board Impedance	148
5.3.9 Board Impedance/Stackup Summary	149
System Design Considerations 6	153
6.1 Power Delivery	153
6.1.1 Terminology and Definitions	153
6.1.2 Intel® 820 Chipset Customer Reference Board Power Delivery	154
6.1.3 64/72Mbit RDRAM Excessive Power Consumption	157
6.1.3.1 Option 1: Reduce the Clock Frequency During Initialization	158
6.1.3.2 Option 2: Increase the Current Capability of the 2.5V Voltage Regulator	158
6.2 Power Plane Splits	159
6.3 Thermal Design Power	159
6.4 Glue Chip 3 (Intel® 820 Chipset Glue Chip)	160
Appendix A: Reference Board Schematics: Uni-Processor	161
Reference Design Schematics: Uni-Processor A	163
Appendix B: Reference Design Schematics: Dual-Processor B	201

Match case Limit results 1 per page

11-29-1999_14:46

VRM

JP16

JP27

JP28

JP29

JP30

RP24

VID1[0]

VID1[1]

VID1[2]

VID1[3]

VID1[4]

VID1[4:0]

R104

VID3_R

VID2_R

VID1_R

VID0_R

R398

10K

R371

VRM_G2

VRM_G1

R71

5.1-5%

OUTEN

VRM_PWRGD

2200UF

C100

C93

2200UF

C103

JP9

JP10

JP7

JP6

JP8

R65

1200UF

C87

C111

1200UF

C107

R55

8.2K

R53

5.6K

R332

220

2.7K

R54

VRM_COMP

VRM_SS

VRM_IFB

VRM_FAULT

VRM_VFB

VRM_COMP_R

C82

1200UF

C366

2200UF

PVCC_R

C72

0.01UF

C90

0.1UF

C73

150PF

C75

0.1UF

C86

0.1UF

10UF

C140

C74

0.01UF

C71

1000PF

1UF-X7R

C118

1UF-X7R

C119

VR3

VRM_IMAX

ETQP6F0R8L

1.0UH-20A

L18

IFB_Q

VRM_VCC5

DO3316P-102

1UH

L19

1UF-X7R

C97

J14

B16

A16

B20

B19

B18

B17

A20

A19

A18

A17

B10

B11

B12

A10

A11

A12

A13

B13

B14

A14

B15

A15

VID1_0R

VID1_2R

VID1_4R

VID1_3R

VRM1_PWRGD

R370

220

VID1_1R

VID[4:0]

VID0

VID1

VID2

VID3

VID4

10K

R80

RP21

VID1_0R

VID1_1R

VID1_2R

VID1_3R

VID1_4R

VID4_R

PCD PLATFORM DESIGN

REV:

DRAWN BY:

LAST REVISED:

PROJECT:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD

3.03

OF 38

VCCVID1

VCC3_3

VCC12

VCC5

VCC12

SI4410DY

VCC3_3

VCC5

VCC12

SI4410DY

LTC1753

SENSE

SGND

GND

VCC

PVCC

COMP

VID4

VID3

VID2

VID1

VID0

OUTEN

IMAX

PWRGD

FAULT#

IFB

VFB

VCCVID

VCCVID1

GND8

V_OUT3

V5_IN3

V5_IN0

V5_IN4

V5_IN5

V5_IN2

V5_IN1

GND10

V_OUT10

GND9

V_OUT9

V_OUT5

GND4

V_OUT4

GND3

V12_IN1

OUT_EN

VID1

VID3

PWR_GOOD

GND5

V_OUT6

GND6

V12_IN0

V12_IN2

ISHARE

VID0

VID2

VID4

V_OUT0

GND0

V_OUT1

GND1

V_OUT7

GND7

V_OUT2

V_OUT8

GND2

VRM8_4

RSV

VCC5

VID Override Jumpers

Sanyo 4SP2200M

No Stuff C106

C118, C119 must be next to FETs.

C82,C87,C107,C111 must support >6A of RMS current.

Place caps next to output FETs.

VRM

VRM requirements are based on VRM8.4 spec .

VID Override Jumpers

Default JP6-JP10 OUT.

Remove RP21, R398 for VID override.

Default JP16, JP27-JP30 OUT.

Remove RP24, R104 for VID override.