Intel VC820 Design Guide - Page 49
VIA Compensation, 2.6.2.8 Length Matching & Via Compensation Example
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Layout/Routing Guidelines 2.6.2.7 VIA Compensation As described in Section 2.8.2, "Strobe Signals" on page 2-44, all signals must have the same number of vias. As a result, each trace will have 1 via (near the BGA pad) because some of the RSL signals must be routed on the bottom of the motherboard. Therefore, it is necessary to place a dummy via on all signals that are routed on the top layer. Because the electrical characteristics of a dummy via do not match the electrical characteristics of a real via exactly, additional compensation must be performed on each signal that has a dummy via. Each signal with a dummy via must have 25 mils of additional trace length. That is: a real via = a dummy via + 25 mils of trace length. This 25 mils of additional trace length must be added to each signal routed on the top layer after length matching, as documented in Section 2.6.2.6, "Length Matching Methods" on page 2-21. Figure 2-24. "Dummy" Via vs. Real "Via" "DUMMY Via" Trace "REAL Via" Trace PCB PCB PCB PCB Via Via Trace 2.6.2.8 Length Matching & Via Compensation Example Table 2-5 can be used to ensure that the RSL signals are the correct length. Note: 2000 mils was chosen as an EXAMPLE Nominal RSL Length. Intel®820 Chipset Design Guide 2-23